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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-28 07:27:34 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-28 07:27:34 -0400
commitf9cef506815386df4bd7e463b59e0a0984ce0355 (patch)
treeb26a202b2f0472e3ebe889012312b115917717f9 /arch/arm/mach-s5pc100
parent9ae21ca362679757786f5abe556c7943e9001426 (diff)
parentcbff3eb3e6e3c618583a7435f87c1548aa12b0ad (diff)
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable
Conflicts: arch/arm/mach-s3c64xx/dev-audio.c
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r--arch/arm/mach-s5pc100/Kconfig1
-rw-r--r--arch/arm/mach-s5pc100/Makefile2
-rw-r--r--arch/arm/mach-s5pc100/clock.c174
-rw-r--r--arch/arm/mach-s5pc100/dev-audio.c86
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c22
-rw-r--r--arch/arm/mach-s5pc100/dma.c4
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c216
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h13
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h49
-rw-r--r--arch/arm/mach-s5pc100/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pc100/irq-gpio.c266
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c4
-rw-r--r--arch/arm/mach-s5pc100/setup-fb-24bpp.c30
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c0.c6
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c1.c6
-rw-r--r--arch/arm/mach-s5pc100/setup-ide.c41
-rw-r--r--arch/arm/mach-s5pc100/setup-keypad.c15
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci-gpio.c35
20 files changed, 306 insertions, 675 deletions
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 77ae4bfb74ba..b8fbf2fcba6f 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -9,7 +9,6 @@ if ARCH_S5PC100
9 9
10config CPU_S5PC100 10config CPU_S5PC100
11 bool 11 bool
12 select PLAT_S5P
13 select S5P_EXT_INT 12 select S5P_EXT_INT
14 select S3C_PL330_DMA 13 select S3C_PL330_DMA
15 help 14 help
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a021ed1fb4b6..eecab57d2e5d 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj- :=
11 11
12# Core support for S5PC100 system 12# Core support for S5PC100 system
13 13
14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o 14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o
15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o 15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
16obj-$(CONFIG_CPU_S5PC100) += dma.o 16obj-$(CONFIG_CPU_S5PC100) += dma.o
17 17
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 084abd13b0a5..2d4a761a5163 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = {
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, 273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
274}; 274};
275 275
276static int s5pc100_epll_enable(struct clk *clk, int enable)
277{
278 unsigned int ctrlbit = clk->ctrlbit;
279 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
280
281 if (enable)
282 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
283 else
284 __raw_writel(epll_con, S5P_EPLL_CON);
285
286 return 0;
287}
288
289static unsigned long s5pc100_epll_get_rate(struct clk *clk)
290{
291 return clk->rate;
292}
293
294static u32 epll_div[][4] = { 276static u32 epll_div[][4] = {
295 { 32750000, 131, 3, 4 }, 277 { 32750000, 131, 3, 4 },
296 { 32768000, 131, 3, 4 }, 278 { 32768000, 131, 3, 4 },
@@ -341,13 +323,16 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
341 323
342 __raw_writel(epll_con, S5P_EPLL_CON); 324 __raw_writel(epll_con, S5P_EPLL_CON);
343 325
326 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
327 clk->rate, rate);
328
344 clk->rate = rate; 329 clk->rate = rate;
345 330
346 return 0; 331 return 0;
347} 332}
348 333
349static struct clk_ops s5pc100_epll_ops = { 334static struct clk_ops s5pc100_epll_ops = {
350 .get_rate = s5pc100_epll_get_rate, 335 .get_rate = s5p_epll_get_rate,
351 .set_rate = s5pc100_epll_set_rate, 336 .set_rate = s5pc100_epll_set_rate,
352}; 337};
353 338
@@ -691,55 +676,55 @@ static struct clk init_clocks_disable[] = {
691 }, { 676 }, {
692 .name = "iis", 677 .name = "iis",
693 .id = 0, 678 .id = 0,
694 .parent = &clk_div_d1_bus.clk, 679 .parent = &clk_div_pclkd1.clk,
695 .enable = s5pc100_d1_5_ctrl, 680 .enable = s5pc100_d1_5_ctrl,
696 .ctrlbit = (1 << 0), 681 .ctrlbit = (1 << 0),
697 }, { 682 }, {
698 .name = "iis", 683 .name = "iis",
699 .id = 1, 684 .id = 1,
700 .parent = &clk_div_d1_bus.clk, 685 .parent = &clk_div_pclkd1.clk,
701 .enable = s5pc100_d1_5_ctrl, 686 .enable = s5pc100_d1_5_ctrl,
702 .ctrlbit = (1 << 1), 687 .ctrlbit = (1 << 1),
703 }, { 688 }, {
704 .name = "iis", 689 .name = "iis",
705 .id = 2, 690 .id = 2,
706 .parent = &clk_div_d1_bus.clk, 691 .parent = &clk_div_pclkd1.clk,
707 .enable = s5pc100_d1_5_ctrl, 692 .enable = s5pc100_d1_5_ctrl,
708 .ctrlbit = (1 << 2), 693 .ctrlbit = (1 << 2),
709 }, { 694 }, {
710 .name = "ac97", 695 .name = "ac97",
711 .id = -1, 696 .id = -1,
712 .parent = &clk_div_d1_bus.clk, 697 .parent = &clk_div_pclkd1.clk,
713 .enable = s5pc100_d1_5_ctrl, 698 .enable = s5pc100_d1_5_ctrl,
714 .ctrlbit = (1 << 3), 699 .ctrlbit = (1 << 3),
715 }, { 700 }, {
716 .name = "pcm", 701 .name = "pcm",
717 .id = 0, 702 .id = 0,
718 .parent = &clk_div_d1_bus.clk, 703 .parent = &clk_div_pclkd1.clk,
719 .enable = s5pc100_d1_5_ctrl, 704 .enable = s5pc100_d1_5_ctrl,
720 .ctrlbit = (1 << 4), 705 .ctrlbit = (1 << 4),
721 }, { 706 }, {
722 .name = "pcm", 707 .name = "pcm",
723 .id = 1, 708 .id = 1,
724 .parent = &clk_div_d1_bus.clk, 709 .parent = &clk_div_pclkd1.clk,
725 .enable = s5pc100_d1_5_ctrl, 710 .enable = s5pc100_d1_5_ctrl,
726 .ctrlbit = (1 << 5), 711 .ctrlbit = (1 << 5),
727 }, { 712 }, {
728 .name = "spdif", 713 .name = "spdif",
729 .id = -1, 714 .id = -1,
730 .parent = &clk_div_d1_bus.clk, 715 .parent = &clk_div_pclkd1.clk,
731 .enable = s5pc100_d1_5_ctrl, 716 .enable = s5pc100_d1_5_ctrl,
732 .ctrlbit = (1 << 6), 717 .ctrlbit = (1 << 6),
733 }, { 718 }, {
734 .name = "adc", 719 .name = "adc",
735 .id = -1, 720 .id = -1,
736 .parent = &clk_div_d1_bus.clk, 721 .parent = &clk_div_pclkd1.clk,
737 .enable = s5pc100_d1_5_ctrl, 722 .enable = s5pc100_d1_5_ctrl,
738 .ctrlbit = (1 << 7), 723 .ctrlbit = (1 << 7),
739 }, { 724 }, {
740 .name = "keypad", 725 .name = "keypad",
741 .id = -1, 726 .id = -1,
742 .parent = &clk_div_d1_bus.clk, 727 .parent = &clk_div_pclkd1.clk,
743 .enable = s5pc100_d1_5_ctrl, 728 .enable = s5pc100_d1_5_ctrl,
744 .ctrlbit = (1 << 8), 729 .ctrlbit = (1 << 8),
745 }, { 730 }, {
@@ -848,6 +833,18 @@ struct clksrc_sources clk_src_group3 = {
848 .nr_sources = ARRAY_SIZE(clk_src_group3_list), 833 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
849}; 834};
850 835
836static struct clksrc_clk clk_sclk_audio0 = {
837 .clk = {
838 .name = "sclk_audio",
839 .id = 0,
840 .ctrlbit = (1 << 8),
841 .enable = s5pc100_sclk1_ctrl,
842 },
843 .sources = &clk_src_group3,
844 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
845 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
846};
847
851static struct clk *clk_src_group4_list[] = { 848static struct clk *clk_src_group4_list[] = {
852 [0] = &clk_mout_epll.clk, 849 [0] = &clk_mout_epll.clk,
853 [1] = &clk_div_mpll.clk, 850 [1] = &clk_div_mpll.clk,
@@ -862,6 +859,18 @@ struct clksrc_sources clk_src_group4 = {
862 .nr_sources = ARRAY_SIZE(clk_src_group4_list), 859 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
863}; 860};
864 861
862static struct clksrc_clk clk_sclk_audio1 = {
863 .clk = {
864 .name = "sclk_audio",
865 .id = 1,
866 .ctrlbit = (1 << 9),
867 .enable = s5pc100_sclk1_ctrl,
868 },
869 .sources = &clk_src_group4,
870 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
871 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
872};
873
865static struct clk *clk_src_group5_list[] = { 874static struct clk *clk_src_group5_list[] = {
866 [0] = &clk_mout_epll.clk, 875 [0] = &clk_mout_epll.clk,
867 [1] = &clk_div_mpll.clk, 876 [1] = &clk_div_mpll.clk,
@@ -875,6 +884,18 @@ struct clksrc_sources clk_src_group5 = {
875 .nr_sources = ARRAY_SIZE(clk_src_group5_list), 884 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
876}; 885};
877 886
887static struct clksrc_clk clk_sclk_audio2 = {
888 .clk = {
889 .name = "sclk_audio",
890 .id = 2,
891 .ctrlbit = (1 << 10),
892 .enable = s5pc100_sclk1_ctrl,
893 },
894 .sources = &clk_src_group5,
895 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
896 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
897};
898
878static struct clk *clk_src_group6_list[] = { 899static struct clk *clk_src_group6_list[] = {
879 [0] = &s5p_clk_27m, 900 [0] = &s5p_clk_27m,
880 [1] = &clk_vclk54m, 901 [1] = &clk_vclk54m,
@@ -944,6 +965,64 @@ struct clksrc_sources clk_src_pwi = {
944 .nr_sources = ARRAY_SIZE(clk_src_pwi_list), 965 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
945}; 966};
946 967
968static struct clk *clk_sclk_spdif_list[] = {
969 [0] = &clk_sclk_audio0.clk,
970 [1] = &clk_sclk_audio1.clk,
971 [2] = &clk_sclk_audio2.clk,
972};
973
974struct clksrc_sources clk_src_sclk_spdif = {
975 .sources = clk_sclk_spdif_list,
976 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
977};
978
979static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
980{
981 struct clk *pclk;
982 int ret;
983
984 pclk = clk_get_parent(clk);
985 if (IS_ERR(pclk))
986 return -EINVAL;
987
988 ret = pclk->ops->set_rate(pclk, rate);
989 clk_put(pclk);
990
991 return ret;
992}
993
994static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
995{
996 struct clk *pclk;
997 int rate;
998
999 pclk = clk_get_parent(clk);
1000 if (IS_ERR(pclk))
1001 return -EINVAL;
1002
1003 rate = pclk->ops->get_rate(clk);
1004 clk_put(pclk);
1005
1006 return rate;
1007}
1008
1009static struct clk_ops s5pc100_sclk_spdif_ops = {
1010 .set_rate = s5pc100_spdif_set_rate,
1011 .get_rate = s5pc100_spdif_get_rate,
1012};
1013
1014static struct clksrc_clk clk_sclk_spdif = {
1015 .clk = {
1016 .name = "sclk_spdif",
1017 .id = -1,
1018 .ctrlbit = (1 << 11),
1019 .enable = s5pc100_sclk1_ctrl,
1020 .ops = &s5pc100_sclk_spdif_ops,
1021 },
1022 .sources = &clk_src_sclk_spdif,
1023 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
1024};
1025
947static struct clksrc_clk clksrcs[] = { 1026static struct clksrc_clk clksrcs[] = {
948 { 1027 {
949 .clk = { 1028 .clk = {
@@ -1001,39 +1080,6 @@ static struct clksrc_clk clksrcs[] = {
1001 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, 1080 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1002 }, { 1081 }, {
1003 .clk = { 1082 .clk = {
1004 .name = "sclk_audio",
1005 .id = 0,
1006 .ctrlbit = (1 << 8),
1007 .enable = s5pc100_sclk1_ctrl,
1008
1009 },
1010 .sources = &clk_src_group3,
1011 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
1012 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1013 }, {
1014 .clk = {
1015 .name = "sclk_audio",
1016 .id = 1,
1017 .ctrlbit = (1 << 9),
1018 .enable = s5pc100_sclk1_ctrl,
1019
1020 },
1021 .sources = &clk_src_group4,
1022 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
1023 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
1024 }, {
1025 .clk = {
1026 .name = "sclk_audio",
1027 .id = 2,
1028 .ctrlbit = (1 << 10),
1029 .enable = s5pc100_sclk1_ctrl,
1030
1031 },
1032 .sources = &clk_src_group5,
1033 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
1034 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
1035 }, {
1036 .clk = {
1037 .name = "sclk_lcd", 1083 .name = "sclk_lcd",
1038 .id = -1, 1084 .id = -1,
1039 .ctrlbit = (1 << 0), 1085 .ctrlbit = (1 << 0),
@@ -1179,6 +1225,10 @@ static struct clksrc_clk *sysclks[] = {
1179 &clk_div_pclkd1, 1225 &clk_div_pclkd1,
1180 &clk_div_cam, 1226 &clk_div_cam,
1181 &clk_div_hdmi, 1227 &clk_div_hdmi,
1228 &clk_sclk_audio0,
1229 &clk_sclk_audio1,
1230 &clk_sclk_audio2,
1231 &clk_sclk_spdif,
1182}; 1232};
1183 1233
1184void __init_or_cpufreq s5pc100_setup_clocks(void) 1234void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1196,7 +1246,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1196 unsigned int ptr; 1246 unsigned int ptr;
1197 1247
1198 /* Set S5PC100 functions for clk_fout_epll */ 1248 /* Set S5PC100 functions for clk_fout_epll */
1199 clk_fout_epll.enable = s5pc100_epll_enable; 1249 clk_fout_epll.enable = s5p_epll_enable;
1200 clk_fout_epll.ops = &s5pc100_epll_ops; 1250 clk_fout_epll.ops = &s5pc100_epll_ops;
1201 1251
1202 printk(KERN_DEBUG "%s: registering clocks\n", __func__); 1252 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index a699ed6acc23..564e195ec493 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -24,19 +24,11 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
24 /* configure GPIO for i2s port */ 24 /* configure GPIO for i2s port */
25 switch (pdev->id) { 25 switch (pdev->id) {
26 case 1: 26 case 1:
27 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2)); 27 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
28 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
29 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
30 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
31 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
32 break; 28 break;
33 29
34 case 2: 30 case 2:
35 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4)); 31 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
36 s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
37 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
38 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
39 s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
40 break; 32 break;
41 33
42 case -1: /* Dedicated pins */ 34 case -1: /* Dedicated pins */
@@ -144,19 +136,11 @@ static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
144{ 136{
145 switch (pdev->id) { 137 switch (pdev->id) {
146 case 0: 138 case 0:
147 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5)); 139 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
148 s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
149 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
150 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
151 s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
152 break; 140 break;
153 141
154 case 1: 142 case 1:
155 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3)); 143 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
156 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
157 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
158 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
159 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
160 break; 144 break;
161 145
162 default: 146 default:
@@ -231,13 +215,7 @@ struct platform_device s5pc100_device_pcm1 = {
231 215
232static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) 216static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
233{ 217{
234 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4)); 218 return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
235 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
236 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
237 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
238 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
239
240 return 0;
241} 219}
242 220
243static struct resource s5pc100_ac97_resource[] = { 221static struct resource s5pc100_ac97_resource[] = {
@@ -285,3 +263,57 @@ struct platform_device s5pc100_device_ac97 = {
285 .coherent_dma_mask = DMA_BIT_MASK(32), 263 .coherent_dma_mask = DMA_BIT_MASK(32),
286 }, 264 },
287}; 265};
266
267/* S/PDIF Controller platform_device */
268static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
269{
270 s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
271
272 return 0;
273}
274
275static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
276{
277 s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
278
279 return 0;
280}
281
282static struct resource s5pc100_spdif_resource[] = {
283 [0] = {
284 .start = S5PC100_PA_SPDIF,
285 .end = S5PC100_PA_SPDIF + 0x100 - 1,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = DMACH_SPDIF,
290 .end = DMACH_SPDIF,
291 .flags = IORESOURCE_DMA,
292 },
293};
294
295static struct s3c_audio_pdata s5p_spdif_pdata = {
296 .cfg_gpio = s5pc100_spdif_cfg_gpd,
297};
298
299static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
300
301struct platform_device s5pc100_device_spdif = {
302 .name = "samsung-spdif",
303 .id = -1,
304 .num_resources = ARRAY_SIZE(s5pc100_spdif_resource),
305 .resource = s5pc100_spdif_resource,
306 .dev = {
307 .platform_data = &s5p_spdif_pdata,
308 .dma_mask = &s5pc100_spdif_dmamask,
309 .coherent_dma_mask = DMA_BIT_MASK(32),
310 },
311};
312
313void __init s5pc100_spdif_setup_gpio(int gpio)
314{
315 if (gpio == S5PC100_SPDIF_GPD)
316 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
317 else
318 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
319}
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
index a0ef7c302c16..57b19794d9bb 100644
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -38,30 +38,20 @@ static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
38{ 38{
39 switch (pdev->id) { 39 switch (pdev->id) {
40 case 0: 40 case 0:
41 s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2)); 41 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
42 s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2)); 42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
44 s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
46 s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
47 break; 43 break;
48 44
49 case 1: 45 case 1:
50 s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2)); 46 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
51 s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2)); 47 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
52 s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
53 s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
54 s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
55 s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
56 break; 48 break;
57 49
58 case 2: 50 case 2:
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); 51 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
61 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
62 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); 52 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
63 s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP); 53 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
64 s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP); 54 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
65 break; 55 break;
66 56
67 default: 57 default:
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 0f5517571e2c..bf4cd0fb97c6 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -81,7 +81,7 @@ static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
81 81
82static struct platform_device s5pc100_device_pdma0 = { 82static struct platform_device s5pc100_device_pdma0 = {
83 .name = "s3c-pl330", 83 .name = "s3c-pl330",
84 .id = 1, 84 .id = 0,
85 .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource), 85 .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource),
86 .resource = s5pc100_pdma0_resource, 86 .resource = s5pc100_pdma0_resource,
87 .dev = { 87 .dev = {
@@ -143,7 +143,7 @@ static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
143 143
144static struct platform_device s5pc100_device_pdma1 = { 144static struct platform_device s5pc100_device_pdma1 = {
145 .name = "s3c-pl330", 145 .name = "s3c-pl330",
146 .id = 2, 146 .id = 1,
147 .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource), 147 .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource),
148 .resource = s5pc100_pdma1_resource, 148 .resource = s5pc100_pdma1_resource,
149 .dev = { 149 .dev = {
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 0fab7f2cd8bf..20856eb7dd51 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -1,5 +1,7 @@
1/* 1/* linux/arch/arm/mach-s5pc100/gpiolib.c
2 * arch/arm/plat-s5pc100/gpiolib.c 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
3 * 5 *
4 * Copyright 2009 Samsung Electronics Co 6 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com> 7 * Kyungmin Park <kyungmin.park@samsung.com>
@@ -61,30 +63,6 @@
61 * L3 8 4Bit None 63 * L3 8 4Bit None
62 */ 64 */
63 65
64static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
65{
66 return S3C_IRQ_GPIO(chip->base + offset);
67}
68
69static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
70{
71 int base;
72
73 base = chip->base - S5PC100_GPH0(0);
74 if (base == 0)
75 return IRQ_EINT(offset);
76 base = chip->base - S5PC100_GPH1(0);
77 if (base == 0)
78 return IRQ_EINT(8 + offset);
79 base = chip->base - S5PC100_GPH2(0);
80 if (base == 0)
81 return IRQ_EINT(16 + offset);
82 base = chip->base - S5PC100_GPH3(0);
83 if (base == 0)
84 return IRQ_EINT(24 + offset);
85 return -EINVAL;
86}
87
88static struct s3c_gpio_cfg gpio_cfg = { 66static struct s3c_gpio_cfg gpio_cfg = {
89 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
90 .set_pull = s3c_gpio_setpull_updown, 68 .set_pull = s3c_gpio_setpull_updown,
@@ -104,209 +82,150 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
104 .get_pull = s3c_gpio_getpull_updown, 82 .get_pull = s3c_gpio_getpull_updown,
105}; 83};
106 84
85/*
86 * GPIO bank's base address given the index of the bank in the
87 * list of all gpio banks.
88 */
89#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
90
91/*
92 * Following are the gpio banks in S5PC100.
93 *
94 * The 'config' member when left to NULL, is initialized to the default
95 * structure gpio_cfg in the init function below.
96 *
97 * The 'base' member is also initialized in the init function below.
98 * Note: The initialization of 'base' member of s3c_gpio_chip structure
99 * uses the above macro and depends on the banks being listed in order here.
100 */
107static struct s3c_gpio_chip s5pc100_gpio_chips[] = { 101static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
108 { 102 {
109 .base = S5PC100_GPA0_BASE,
110 .config = &gpio_cfg,
111 .chip = { 103 .chip = {
112 .base = S5PC100_GPA0(0), 104 .base = S5PC100_GPA0(0),
113 .ngpio = S5PC100_GPIO_A0_NR, 105 .ngpio = S5PC100_GPIO_A0_NR,
114 .label = "GPA0", 106 .label = "GPA0",
115 }, 107 },
116 }, { 108 }, {
117 .base = S5PC100_GPA1_BASE,
118 .config = &gpio_cfg,
119 .chip = { 109 .chip = {
120 .base = S5PC100_GPA1(0), 110 .base = S5PC100_GPA1(0),
121 .ngpio = S5PC100_GPIO_A1_NR, 111 .ngpio = S5PC100_GPIO_A1_NR,
122 .label = "GPA1", 112 .label = "GPA1",
123 }, 113 },
124 }, { 114 }, {
125 .base = S5PC100_GPB_BASE,
126 .config = &gpio_cfg,
127 .chip = { 115 .chip = {
128 .base = S5PC100_GPB(0), 116 .base = S5PC100_GPB(0),
129 .ngpio = S5PC100_GPIO_B_NR, 117 .ngpio = S5PC100_GPIO_B_NR,
130 .label = "GPB", 118 .label = "GPB",
131 }, 119 },
132 }, { 120 }, {
133 .base = S5PC100_GPC_BASE,
134 .config = &gpio_cfg,
135 .chip = { 121 .chip = {
136 .base = S5PC100_GPC(0), 122 .base = S5PC100_GPC(0),
137 .ngpio = S5PC100_GPIO_C_NR, 123 .ngpio = S5PC100_GPIO_C_NR,
138 .label = "GPC", 124 .label = "GPC",
139 }, 125 },
140 }, { 126 }, {
141 .base = S5PC100_GPD_BASE,
142 .config = &gpio_cfg,
143 .chip = { 127 .chip = {
144 .base = S5PC100_GPD(0), 128 .base = S5PC100_GPD(0),
145 .ngpio = S5PC100_GPIO_D_NR, 129 .ngpio = S5PC100_GPIO_D_NR,
146 .label = "GPD", 130 .label = "GPD",
147 }, 131 },
148 }, { 132 }, {
149 .base = S5PC100_GPE0_BASE,
150 .config = &gpio_cfg,
151 .chip = { 133 .chip = {
152 .base = S5PC100_GPE0(0), 134 .base = S5PC100_GPE0(0),
153 .ngpio = S5PC100_GPIO_E0_NR, 135 .ngpio = S5PC100_GPIO_E0_NR,
154 .label = "GPE0", 136 .label = "GPE0",
155 }, 137 },
156 }, { 138 }, {
157 .base = S5PC100_GPE1_BASE,
158 .config = &gpio_cfg,
159 .chip = { 139 .chip = {
160 .base = S5PC100_GPE1(0), 140 .base = S5PC100_GPE1(0),
161 .ngpio = S5PC100_GPIO_E1_NR, 141 .ngpio = S5PC100_GPIO_E1_NR,
162 .label = "GPE1", 142 .label = "GPE1",
163 }, 143 },
164 }, { 144 }, {
165 .base = S5PC100_GPF0_BASE,
166 .config = &gpio_cfg,
167 .chip = { 145 .chip = {
168 .base = S5PC100_GPF0(0), 146 .base = S5PC100_GPF0(0),
169 .ngpio = S5PC100_GPIO_F0_NR, 147 .ngpio = S5PC100_GPIO_F0_NR,
170 .label = "GPF0", 148 .label = "GPF0",
171 }, 149 },
172 }, { 150 }, {
173 .base = S5PC100_GPF1_BASE,
174 .config = &gpio_cfg,
175 .chip = { 151 .chip = {
176 .base = S5PC100_GPF1(0), 152 .base = S5PC100_GPF1(0),
177 .ngpio = S5PC100_GPIO_F1_NR, 153 .ngpio = S5PC100_GPIO_F1_NR,
178 .label = "GPF1", 154 .label = "GPF1",
179 }, 155 },
180 }, { 156 }, {
181 .base = S5PC100_GPF2_BASE,
182 .config = &gpio_cfg,
183 .chip = { 157 .chip = {
184 .base = S5PC100_GPF2(0), 158 .base = S5PC100_GPF2(0),
185 .ngpio = S5PC100_GPIO_F2_NR, 159 .ngpio = S5PC100_GPIO_F2_NR,
186 .label = "GPF2", 160 .label = "GPF2",
187 }, 161 },
188 }, { 162 }, {
189 .base = S5PC100_GPF3_BASE,
190 .config = &gpio_cfg,
191 .chip = { 163 .chip = {
192 .base = S5PC100_GPF3(0), 164 .base = S5PC100_GPF3(0),
193 .ngpio = S5PC100_GPIO_F3_NR, 165 .ngpio = S5PC100_GPIO_F3_NR,
194 .label = "GPF3", 166 .label = "GPF3",
195 }, 167 },
196 }, { 168 }, {
197 .base = S5PC100_GPG0_BASE,
198 .config = &gpio_cfg,
199 .chip = { 169 .chip = {
200 .base = S5PC100_GPG0(0), 170 .base = S5PC100_GPG0(0),
201 .ngpio = S5PC100_GPIO_G0_NR, 171 .ngpio = S5PC100_GPIO_G0_NR,
202 .label = "GPG0", 172 .label = "GPG0",
203 }, 173 },
204 }, { 174 }, {
205 .base = S5PC100_GPG1_BASE,
206 .config = &gpio_cfg,
207 .chip = { 175 .chip = {
208 .base = S5PC100_GPG1(0), 176 .base = S5PC100_GPG1(0),
209 .ngpio = S5PC100_GPIO_G1_NR, 177 .ngpio = S5PC100_GPIO_G1_NR,
210 .label = "GPG1", 178 .label = "GPG1",
211 }, 179 },
212 }, { 180 }, {
213 .base = S5PC100_GPG2_BASE,
214 .config = &gpio_cfg,
215 .chip = { 181 .chip = {
216 .base = S5PC100_GPG2(0), 182 .base = S5PC100_GPG2(0),
217 .ngpio = S5PC100_GPIO_G2_NR, 183 .ngpio = S5PC100_GPIO_G2_NR,
218 .label = "GPG2", 184 .label = "GPG2",
219 }, 185 },
220 }, { 186 }, {
221 .base = S5PC100_GPG3_BASE,
222 .config = &gpio_cfg,
223 .chip = { 187 .chip = {
224 .base = S5PC100_GPG3(0), 188 .base = S5PC100_GPG3(0),
225 .ngpio = S5PC100_GPIO_G3_NR, 189 .ngpio = S5PC100_GPIO_G3_NR,
226 .label = "GPG3", 190 .label = "GPG3",
227 }, 191 },
228 }, { 192 }, {
229 .base = S5PC100_GPH0_BASE,
230 .config = &gpio_cfg_eint,
231 .chip = {
232 .base = S5PC100_GPH0(0),
233 .ngpio = S5PC100_GPIO_H0_NR,
234 .label = "GPH0",
235 },
236 }, {
237 .base = S5PC100_GPH1_BASE,
238 .config = &gpio_cfg_eint,
239 .chip = {
240 .base = S5PC100_GPH1(0),
241 .ngpio = S5PC100_GPIO_H1_NR,
242 .label = "GPH1",
243 },
244 }, {
245 .base = S5PC100_GPH2_BASE,
246 .config = &gpio_cfg_eint,
247 .chip = {
248 .base = S5PC100_GPH2(0),
249 .ngpio = S5PC100_GPIO_H2_NR,
250 .label = "GPH2",
251 },
252 }, {
253 .base = S5PC100_GPH3_BASE,
254 .config = &gpio_cfg_eint,
255 .chip = {
256 .base = S5PC100_GPH3(0),
257 .ngpio = S5PC100_GPIO_H3_NR,
258 .label = "GPH3",
259 },
260 }, {
261 .base = S5PC100_GPI_BASE,
262 .config = &gpio_cfg,
263 .chip = { 193 .chip = {
264 .base = S5PC100_GPI(0), 194 .base = S5PC100_GPI(0),
265 .ngpio = S5PC100_GPIO_I_NR, 195 .ngpio = S5PC100_GPIO_I_NR,
266 .label = "GPI", 196 .label = "GPI",
267 }, 197 },
268 }, { 198 }, {
269 .base = S5PC100_GPJ0_BASE,
270 .config = &gpio_cfg,
271 .chip = { 199 .chip = {
272 .base = S5PC100_GPJ0(0), 200 .base = S5PC100_GPJ0(0),
273 .ngpio = S5PC100_GPIO_J0_NR, 201 .ngpio = S5PC100_GPIO_J0_NR,
274 .label = "GPJ0", 202 .label = "GPJ0",
275 }, 203 },
276 }, { 204 }, {
277 .base = S5PC100_GPJ1_BASE,
278 .config = &gpio_cfg,
279 .chip = { 205 .chip = {
280 .base = S5PC100_GPJ1(0), 206 .base = S5PC100_GPJ1(0),
281 .ngpio = S5PC100_GPIO_J1_NR, 207 .ngpio = S5PC100_GPIO_J1_NR,
282 .label = "GPJ1", 208 .label = "GPJ1",
283 }, 209 },
284 }, { 210 }, {
285 .base = S5PC100_GPJ2_BASE,
286 .config = &gpio_cfg,
287 .chip = { 211 .chip = {
288 .base = S5PC100_GPJ2(0), 212 .base = S5PC100_GPJ2(0),
289 .ngpio = S5PC100_GPIO_J2_NR, 213 .ngpio = S5PC100_GPIO_J2_NR,
290 .label = "GPJ2", 214 .label = "GPJ2",
291 }, 215 },
292 }, { 216 }, {
293 .base = S5PC100_GPJ3_BASE,
294 .config = &gpio_cfg,
295 .chip = { 217 .chip = {
296 .base = S5PC100_GPJ3(0), 218 .base = S5PC100_GPJ3(0),
297 .ngpio = S5PC100_GPIO_J3_NR, 219 .ngpio = S5PC100_GPIO_J3_NR,
298 .label = "GPJ3", 220 .label = "GPJ3",
299 }, 221 },
300 }, { 222 }, {
301 .base = S5PC100_GPJ4_BASE,
302 .config = &gpio_cfg,
303 .chip = { 223 .chip = {
304 .base = S5PC100_GPJ4(0), 224 .base = S5PC100_GPJ4(0),
305 .ngpio = S5PC100_GPIO_J4_NR, 225 .ngpio = S5PC100_GPIO_J4_NR,
306 .label = "GPJ4", 226 .label = "GPJ4",
307 }, 227 },
308 }, { 228 }, {
309 .base = S5PC100_GPK0_BASE,
310 .config = &gpio_cfg_noint, 229 .config = &gpio_cfg_noint,
311 .chip = { 230 .chip = {
312 .base = S5PC100_GPK0(0), 231 .base = S5PC100_GPK0(0),
@@ -314,7 +233,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
314 .label = "GPK0", 233 .label = "GPK0",
315 }, 234 },
316 }, { 235 }, {
317 .base = S5PC100_GPK1_BASE,
318 .config = &gpio_cfg_noint, 236 .config = &gpio_cfg_noint,
319 .chip = { 237 .chip = {
320 .base = S5PC100_GPK1(0), 238 .base = S5PC100_GPK1(0),
@@ -322,7 +240,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
322 .label = "GPK1", 240 .label = "GPK1",
323 }, 241 },
324 }, { 242 }, {
325 .base = S5PC100_GPK2_BASE,
326 .config = &gpio_cfg_noint, 243 .config = &gpio_cfg_noint,
327 .chip = { 244 .chip = {
328 .base = S5PC100_GPK2(0), 245 .base = S5PC100_GPK2(0),
@@ -330,7 +247,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
330 .label = "GPK2", 247 .label = "GPK2",
331 }, 248 },
332 }, { 249 }, {
333 .base = S5PC100_GPK3_BASE,
334 .config = &gpio_cfg_noint, 250 .config = &gpio_cfg_noint,
335 .chip = { 251 .chip = {
336 .base = S5PC100_GPK3(0), 252 .base = S5PC100_GPK3(0),
@@ -338,7 +254,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
338 .label = "GPK3", 254 .label = "GPK3",
339 }, 255 },
340 }, { 256 }, {
341 .base = S5PC100_GPL0_BASE,
342 .config = &gpio_cfg_noint, 257 .config = &gpio_cfg_noint,
343 .chip = { 258 .chip = {
344 .base = S5PC100_GPL0(0), 259 .base = S5PC100_GPL0(0),
@@ -346,7 +261,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
346 .label = "GPL0", 261 .label = "GPL0",
347 }, 262 },
348 }, { 263 }, {
349 .base = S5PC100_GPL1_BASE,
350 .config = &gpio_cfg_noint, 264 .config = &gpio_cfg_noint,
351 .chip = { 265 .chip = {
352 .base = S5PC100_GPL1(0), 266 .base = S5PC100_GPL1(0),
@@ -354,7 +268,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
354 .label = "GPL1", 268 .label = "GPL1",
355 }, 269 },
356 }, { 270 }, {
357 .base = S5PC100_GPL2_BASE,
358 .config = &gpio_cfg_noint, 271 .config = &gpio_cfg_noint,
359 .chip = { 272 .chip = {
360 .base = S5PC100_GPL2(0), 273 .base = S5PC100_GPL2(0),
@@ -362,7 +275,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
362 .label = "GPL2", 275 .label = "GPL2",
363 }, 276 },
364 }, { 277 }, {
365 .base = S5PC100_GPL3_BASE,
366 .config = &gpio_cfg_noint, 278 .config = &gpio_cfg_noint,
367 .chip = { 279 .chip = {
368 .base = S5PC100_GPL3(0), 280 .base = S5PC100_GPL3(0),
@@ -370,56 +282,72 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
370 .label = "GPL3", 282 .label = "GPL3",
371 }, 283 },
372 }, { 284 }, {
373 .base = S5PC100_GPL4_BASE,
374 .config = &gpio_cfg_noint, 285 .config = &gpio_cfg_noint,
375 .chip = { 286 .chip = {
376 .base = S5PC100_GPL4(0), 287 .base = S5PC100_GPL4(0),
377 .ngpio = S5PC100_GPIO_L4_NR, 288 .ngpio = S5PC100_GPIO_L4_NR,
378 .label = "GPL4", 289 .label = "GPL4",
379 }, 290 },
291 }, {
292 .base = (S5P_VA_GPIO + 0xC00),
293 .config = &gpio_cfg_eint,
294 .irq_base = IRQ_EINT(0),
295 .chip = {
296 .base = S5PC100_GPH0(0),
297 .ngpio = S5PC100_GPIO_H0_NR,
298 .label = "GPH0",
299 .to_irq = samsung_gpiolib_to_irq,
300 },
301 }, {
302 .base = (S5P_VA_GPIO + 0xC20),
303 .config = &gpio_cfg_eint,
304 .irq_base = IRQ_EINT(8),
305 .chip = {
306 .base = S5PC100_GPH1(0),
307 .ngpio = S5PC100_GPIO_H1_NR,
308 .label = "GPH1",
309 .to_irq = samsung_gpiolib_to_irq,
310 },
311 }, {
312 .base = (S5P_VA_GPIO + 0xC40),
313 .config = &gpio_cfg_eint,
314 .irq_base = IRQ_EINT(16),
315 .chip = {
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
318 .label = "GPH2",
319 .to_irq = samsung_gpiolib_to_irq,
320 },
321 }, {
322 .base = (S5P_VA_GPIO + 0xC60),
323 .config = &gpio_cfg_eint,
324 .irq_base = IRQ_EINT(24),
325 .chip = {
326 .base = S5PC100_GPH3(0),
327 .ngpio = S5PC100_GPIO_H3_NR,
328 .label = "GPH3",
329 .to_irq = samsung_gpiolib_to_irq,
330 },
380 }, 331 },
381}; 332};
382 333
383/* FIXME move from irq-gpio.c */ 334static __init int s5pc100_gpiolib_init(void)
384extern struct irq_chip s5pc100_gpioint;
385extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
386
387static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
388{ 335{
389 /* Interrupt */ 336 struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
390 if (chip->config == &gpio_cfg) { 337 int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
391 int i, irq; 338 int gpioint_group = 0;
392 339 int i;
393 chip->chip.to_irq = s5pc100_gpiolib_to_irq;
394 340
395 for (i = 0; i < chip->chip.ngpio; i++) { 341 for (i = 0; i < nr_chips; i++, chip++) {
396 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; 342 if (chip->config == NULL) {
397 set_irq_chip(irq, &s5pc100_gpioint); 343 chip->config = &gpio_cfg;
398 set_irq_data(irq, &chip->chip); 344 chip->group = gpioint_group++;
399 set_irq_handler(irq, handle_level_irq);
400 set_irq_flags(irq, IRQF_VALID);
401 } 345 }
402 } else if (chip->config == &gpio_cfg_eint) { 346 if (chip->base == NULL)
403 chip->chip.to_irq = s5pc100_gpiolib_to_eint; 347 chip->base = S5PC100_BANK_BASE(i);
404 } 348 }
405}
406
407static __init int s5pc100_gpiolib_init(void)
408{
409 struct s3c_gpio_chip *chip;
410 int nr_chips;
411
412 chip = s5pc100_gpio_chips;
413 nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
414
415 for (; nr_chips > 0; nr_chips--, chip++)
416 s5pc100_gpiolib_link(chip);
417
418 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
419 ARRAY_SIZE(s5pc100_gpio_chips));
420 349
421 /* Interrupt */ 350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
422 set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
423 351
424 return 0; 352 return 0;
425} 353}
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 71ae1f52df1d..29a8a12d9b4f 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,13 +146,6 @@ enum s5p_gpio_number {
146/* define the number of gpios we need to the one after the MP04() range */ 146/* define the number of gpios we need to the one after the MP04() range */
147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) 147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
148 148
149#define EINT_MODE S3C_GPIO_SFN(0x2)
150
151#define EINT_GPIO_0(x) S5PC100_GPH0(x)
152#define EINT_GPIO_1(x) S5PC100_GPH1(x)
153#define EINT_GPIO_2(x) S5PC100_GPH2(x)
154#define EINT_GPIO_3(x) S5PC100_GPH3(x)
155
156#include <asm-generic/gpio.h> 149#include <asm-generic/gpio.h>
157 150
158#endif /* __ASM_ARCH_GPIO_H */ 151#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 06513e647242..d2eb4757381f 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -48,8 +48,8 @@
48#define IRQ_SPI1 S5P_IRQ_VIC1(16) 48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17) 49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18) 50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_CAN0 S5P_IRQ_VIC1(19) 51#define IRQ_IIC2 S5P_IRQ_VIC1(19)
52#define IRQ_CAN1 S5P_IRQ_VIC1(20) 52#define IRQ_IIC3 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21) 53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22) 54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23) 55#define IRQ_UHOST S5P_IRQ_VIC1(23)
@@ -100,11 +100,12 @@
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102 102
103#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) 103/* GPIO interrupt */
104#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) 104#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
105#define S5P_GPIOINT_GROUP_MAXNR 21
105 106
106/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */ 107/* Set the default NR_IRQS */
107#define NR_IRQS (S3C_IRQ_GPIO(320) + 1) 108#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
108 109
109/* Compatibility */ 110/* Compatibility */
110#define IRQ_LCD_FIFO IRQ_LCD0 111#define IRQ_LCD_FIFO IRQ_LCD0
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 8751ef4a6804..32e9cab5c864 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -110,6 +110,8 @@
110#define S5PC100_PA_PCM0 0xF2400000 110#define S5PC100_PA_PCM0 0xF2400000
111#define S5PC100_PA_PCM1 0xF2500000 111#define S5PC100_PA_PCM1 0xF2500000
112 112
113#define S5PC100_PA_SPDIF 0xF2600000
114
113#define S5PC100_PA_TSADC (0xF3000000) 115#define S5PC100_PA_TSADC (0xF3000000)
114 116
115/* KEYPAD */ 117/* KEYPAD */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index dd6295e1251d..0bf73209ec7b 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -11,43 +11,6 @@
11 11
12#include <mach/map.h> 12#include <mach/map.h>
13 13
14/* S5PC100 */
15#define S5PC100_GPIO_BASE S5P_VA_GPIO
16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
19#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
20#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
21#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
22#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
23#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
24#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
25#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
26#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
27#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
28#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
29#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
30#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
31#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
32#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
33#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
34#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
35#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
36#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
37#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
38#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
39#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
40#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
41#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
42#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
43#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
44#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
45#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
46#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50
51#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) 14#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
52#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) 15#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
53 16
@@ -64,12 +27,12 @@
64 27
65#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) 28#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
66 29
67/* values for S5P_EXTINT0 */ 30#define EINT_MODE S3C_GPIO_SFN(0x2)
68#define S5P_EXTINT_LOWLEV (0x00) 31
69#define S5P_EXTINT_HILEV (0x01) 32#define EINT_GPIO_0(x) S5PC100_GPH0(x)
70#define S5P_EXTINT_FALLEDGE (0x02) 33#define EINT_GPIO_1(x) S5PC100_GPH1(x)
71#define S5P_EXTINT_RISEEDGE (0x03) 34#define EINT_GPIO_2(x) S5PC100_GPH2(x)
72#define S5P_EXTINT_BOTHEDGE (0x04) 35#define EINT_GPIO_3(x) S5PC100_GPH3(x)
73 36
74#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ 37#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
75 38
diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
index be9df79903ed..44c8e5726d9d 100644
--- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
12#ifndef __ASM_ARCH_VMALLOC_H 12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H 13#define __ASM_ARCH_VMALLOC_H
14 14
15#define VMALLOC_END (0xe0000000UL) 15#define VMALLOC_END 0xF6000000UL
16 16
17#endif /* __ASM_ARCH_VMALLOC_H */ 17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
deleted file mode 100644
index 2bf86c18bc73..000000000000
--- a/arch/arm/mach-s5pc100/irq-gpio.c
+++ /dev/null
@@ -1,266 +0,0 @@
1/*
2 * arch/arm/mach-s5pc100/irq-gpio.c
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 *
6 * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <mach/map.h>
20#include <plat/gpio-cfg.h>
21
22#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
23
24#define CON_OFFSET 0x700
25#define MASK_OFFSET 0x900
26#define PEND_OFFSET 0xA00
27#define CON_OFFSET_2 0xE00
28#define MASK_OFFSET_2 0xF00
29#define PEND_OFFSET_2 0xF40
30
31#define GPIOINT_LEVEL_LOW 0x0
32#define GPIOINT_LEVEL_HIGH 0x1
33#define GPIOINT_EDGE_FALLING 0x2
34#define GPIOINT_EDGE_RISING 0x3
35#define GPIOINT_EDGE_BOTH 0x4
36
37static int group_to_con_offset(int group)
38{
39 return group << 2;
40}
41
42static int group_to_mask_offset(int group)
43{
44 return group << 2;
45}
46
47static int group_to_pend_offset(int group)
48{
49 return group << 2;
50}
51
52static int s5pc100_get_start(unsigned int group)
53{
54 switch (group) {
55 case 0: return S5PC100_GPIO_A0_START;
56 case 1: return S5PC100_GPIO_A1_START;
57 case 2: return S5PC100_GPIO_B_START;
58 case 3: return S5PC100_GPIO_C_START;
59 case 4: return S5PC100_GPIO_D_START;
60 case 5: return S5PC100_GPIO_E0_START;
61 case 6: return S5PC100_GPIO_E1_START;
62 case 7: return S5PC100_GPIO_F0_START;
63 case 8: return S5PC100_GPIO_F1_START;
64 case 9: return S5PC100_GPIO_F2_START;
65 case 10: return S5PC100_GPIO_F3_START;
66 case 11: return S5PC100_GPIO_G0_START;
67 case 12: return S5PC100_GPIO_G1_START;
68 case 13: return S5PC100_GPIO_G2_START;
69 case 14: return S5PC100_GPIO_G3_START;
70 case 15: return S5PC100_GPIO_I_START;
71 case 16: return S5PC100_GPIO_J0_START;
72 case 17: return S5PC100_GPIO_J1_START;
73 case 18: return S5PC100_GPIO_J2_START;
74 case 19: return S5PC100_GPIO_J3_START;
75 case 20: return S5PC100_GPIO_J4_START;
76 default:
77 BUG();
78 }
79
80 return -EINVAL;
81}
82
83static int s5pc100_get_group(unsigned int irq)
84{
85 irq -= S3C_IRQ_GPIO(0);
86
87 switch (irq) {
88 case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
89 return 0;
90 case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
91 return 1;
92 case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
93 return 2;
94 case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
95 return 3;
96 case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
97 return 4;
98 case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
99 return 5;
100 case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
101 return 6;
102 case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
103 return 7;
104 case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
105 return 8;
106 case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
107 return 9;
108 case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
109 return 10;
110 case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
111 return 11;
112 case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
113 return 12;
114 case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
115 return 13;
116 case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
117 return 14;
118 case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
119 return 15;
120 case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
121 return 16;
122 case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
123 return 17;
124 case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
125 return 18;
126 case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
127 return 19;
128 case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
129 return 20;
130 default:
131 BUG();
132 }
133
134 return -EINVAL;
135}
136
137static int s5pc100_get_offset(unsigned int irq)
138{
139 struct gpio_chip *chip = get_irq_data(irq);
140 return irq - S3C_IRQ_GPIO(chip->base);
141}
142
143static void s5pc100_gpioint_ack(unsigned int irq)
144{
145 int group, offset, pend_offset;
146 unsigned int value;
147
148 group = s5pc100_get_group(irq);
149 offset = s5pc100_get_offset(irq);
150 pend_offset = group_to_pend_offset(group);
151
152 value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
153 value |= 1 << offset;
154 __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
155}
156
157static void s5pc100_gpioint_mask(unsigned int irq)
158{
159 int group, offset, mask_offset;
160 unsigned int value;
161
162 group = s5pc100_get_group(irq);
163 offset = s5pc100_get_offset(irq);
164 mask_offset = group_to_mask_offset(group);
165
166 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
167 value |= 1 << offset;
168 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
169}
170
171static void s5pc100_gpioint_unmask(unsigned int irq)
172{
173 int group, offset, mask_offset;
174 unsigned int value;
175
176 group = s5pc100_get_group(irq);
177 offset = s5pc100_get_offset(irq);
178 mask_offset = group_to_mask_offset(group);
179
180 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
181 value &= ~(1 << offset);
182 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
183}
184
185static void s5pc100_gpioint_mask_ack(unsigned int irq)
186{
187 s5pc100_gpioint_mask(irq);
188 s5pc100_gpioint_ack(irq);
189}
190
191static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
192{
193 int group, offset, con_offset;
194 unsigned int value;
195
196 group = s5pc100_get_group(irq);
197 offset = s5pc100_get_offset(irq);
198 con_offset = group_to_con_offset(group);
199
200 switch (type) {
201 case IRQ_TYPE_NONE:
202 printk(KERN_WARNING "No irq type\n");
203 return -EINVAL;
204 case IRQ_TYPE_EDGE_RISING:
205 type = GPIOINT_EDGE_RISING;
206 break;
207 case IRQ_TYPE_EDGE_FALLING:
208 type = GPIOINT_EDGE_FALLING;
209 break;
210 case IRQ_TYPE_EDGE_BOTH:
211 type = GPIOINT_EDGE_BOTH;
212 break;
213 case IRQ_TYPE_LEVEL_HIGH:
214 type = GPIOINT_LEVEL_HIGH;
215 break;
216 case IRQ_TYPE_LEVEL_LOW:
217 type = GPIOINT_LEVEL_LOW;
218 break;
219 default:
220 BUG();
221 }
222
223
224 value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
225 value &= ~(0xf << (offset * 0x4));
226 value |= (type << (offset * 0x4));
227 __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
228
229 return 0;
230}
231
232struct irq_chip s5pc100_gpioint = {
233 .name = "GPIO",
234 .ack = s5pc100_gpioint_ack,
235 .mask = s5pc100_gpioint_mask,
236 .mask_ack = s5pc100_gpioint_mask_ack,
237 .unmask = s5pc100_gpioint_unmask,
238 .set_type = s5pc100_gpioint_set_type,
239};
240
241void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
242{
243 int group, offset, pend_offset, mask_offset;
244 int real_irq, group_end;
245 unsigned int pend, mask;
246
247 group_end = 21;
248
249 for (group = 0; group < group_end; group++) {
250 pend_offset = group_to_pend_offset(group);
251 pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
252 if (!pend)
253 continue;
254
255 mask_offset = group_to_mask_offset(group);
256 mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
257 pend &= ~mask;
258
259 for (offset = 0; offset < 8; offset++) {
260 if (pend & (1 << offset)) {
261 real_irq = s5pc100_get_start(group) + offset;
262 generic_handle_irq(S3C_IRQ_GPIO(real_irq));
263 }
264 }
265 }
266}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 880fb075092c..18b405d514d6 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -47,6 +47,7 @@
47#include <plat/adc.h> 47#include <plat/adc.h>
48#include <plat/keypad.h> 48#include <plat/keypad.h>
49#include <plat/ts.h> 49#include <plat/ts.h>
50#include <plat/audio.h>
50 51
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 52/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -196,6 +197,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
196 &s5p_device_fimc0, 197 &s5p_device_fimc0,
197 &s5p_device_fimc1, 198 &s5p_device_fimc1,
198 &s5p_device_fimc2, 199 &s5p_device_fimc2,
200 &s5pc100_device_spdif,
199}; 201};
200 202
201static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { 203static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
@@ -226,6 +228,8 @@ static void __init smdkc100_machine_init(void)
226 228
227 samsung_keypad_set_platdata(&smdkc100_keypad_data); 229 samsung_keypad_set_platdata(&smdkc100_keypad_data);
228 230
231 s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
232
229 /* LCD init */ 233 /* LCD init */
230 gpio_request(S5PC100_GPD(0), "GPD"); 234 gpio_request(S5PC100_GPD(0), "GPD");
231 gpio_request(S5PC100_GPH0(6), "GPH0"); 235 gpio_request(S5PC100_GPH0(6), "GPH0");
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
index 6eba6cb8e2f4..d31c0f3fe222 100644
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
@@ -22,27 +22,15 @@
22 22
23#define DISR_OFFSET 0x7008 23#define DISR_OFFSET 0x7008
24 24
25void s5pc100_fb_gpio_setup_24bpp(void) 25static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
26{ 26{
27 unsigned int gpio = 0; 27 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
28 28}
29 for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
30 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
31 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
32 }
33
34 for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
35 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
36 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
37 }
38
39 for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
40 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
41 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
42 }
43 29
44 for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) { 30void s5pc100_fb_gpio_setup_24bpp(void)
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 31{
46 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 32 s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
47 } 33 s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
34 s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
35 s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
48} 36}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
index dd3174e6ecc5..eaef7a3bda49 100644
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
23 23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev) 24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{ 25{
26 s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2)); 26 s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
27 s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP); 27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
30} 28}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
index d1fec26b69ee..aaff74a90dee 100644
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
23 23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev) 24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{ 25{
26 s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2)); 26 s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
27 s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP); 27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
30} 28}
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
index 83575671fb59..223aae044466 100644
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ b/arch/arm/mach-s5pc100/setup-ide.c
@@ -17,52 +17,39 @@
17#include <mach/regs-clock.h> 17#include <mach/regs-clock.h>
18#include <plat/gpio-cfg.h> 18#include <plat/gpio-cfg.h>
19 19
20static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
21{
22 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
23
24 for (; nr > 0; nr--, base++)
25 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
26}
27
20void s5pc100_ide_setup_gpio(void) 28void s5pc100_ide_setup_gpio(void)
21{ 29{
22 u32 reg; 30 u32 reg;
23 u32 gpio = 0;
24 31
25 /* Independent CF interface, CF chip select configuration */ 32 /* Independent CF interface, CF chip select configuration */
26 reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); 33 reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
27 writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); 34 writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
28 35
29 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ 36 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
30 for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) { 37 s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
34 }
35 38
36 /*CF_Data[0 - 7] */ 39 /*CF_Data[0 - 7] */
37 for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) { 40 s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
38 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
39 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
40 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
41 }
42 41
43 /* CF_Data[8 - 15] */ 42 /* CF_Data[8 - 15] */
44 for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) { 43 s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
46 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
47 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
48 }
49 44
50 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ 45 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
51 for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) { 46 s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
52 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
53 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
54 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
55 }
56 47
57 /* EBI_OE, EBI_WE */ 48 /* EBI_OE, EBI_WE */
58 for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++) 49 s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
59 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
60 50
61 /* CF_OE, CF_WE */ 51 /* CF_OE, CF_WE */
62 for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) { 52 s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
63 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
64 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
65 }
66 53
67 /* CF_CD */ 54 /* CF_CD */
68 s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); 55 s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
index d0837a72a58e..ada377f0c206 100644
--- a/arch/arm/mach-s5pc100/setup-keypad.c
+++ b/arch/arm/mach-s5pc100/setup-keypad.c
@@ -15,20 +15,9 @@
15 15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) 16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{ 17{
18 unsigned int gpio;
19 unsigned int end;
20
21 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ 18 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
22 end = S5PC100_GPH3(rows); 19 s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
23 for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
24 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
25 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
26 }
27 20
28 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ 21 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
29 end = S5PC100_GPH2(cols); 22 s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
30 for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 }
34} 23}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index dc7208c639ea..03c02d04c68c 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -25,8 +25,6 @@
25void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) 25void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
26{ 26{
27 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 27 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
28 unsigned int gpio;
29 unsigned int end;
30 unsigned int num; 28 unsigned int num;
31 29
32 num = width; 30 num = width;
@@ -34,20 +32,11 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
34 if (width == 8) 32 if (width == 8)
35 num = width - 2; 33 num = width - 2;
36 34
37 end = S5PC100_GPG0(2 + num);
38
39 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */ 35 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
40 for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) { 36 s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
41 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
42 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
43 }
44 37
45 if (width == 8) { 38 if (width == 8)
46 for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) { 39 s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
47 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
49 }
50 }
51 40
52 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 41 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
53 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); 42 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
@@ -58,16 +47,9 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
58void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) 47void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
59{ 48{
60 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 49 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
61 unsigned int gpio;
62 unsigned int end;
63
64 end = S5PC100_GPG2(2 + width);
65 50
66 /* Set all the necessary GPG2 pins to special-function 2 */ 51 /* Set all the necessary GPG2 pins to special-function 2 */
67 for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) { 52 s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
68 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
69 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
70 }
71 53
72 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 54 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
73 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); 55 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
@@ -78,16 +60,9 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
78void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) 60void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
79{ 61{
80 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 62 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
81 unsigned int gpio;
82 unsigned int end;
83
84 end = S5PC100_GPG3(2 + width);
85 63
86 /* Set all the necessary GPG3 pins to special-function 2 */ 64 /* Set all the necessary GPG3 pins to special-function 2 */
87 for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) { 65 s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
88 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
89 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
90 }
91 66
92 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 67 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
93 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); 68 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:57:58 -0500