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authorMarek Szyprowski <m.szyprowski@samsung.com>2010-05-20 01:51:10 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-20 02:28:44 -0400
commit80dfd9556a94fe479fde86370713aafd33b61a0c (patch)
tree835121842ddb0af778917324869f242d7541d536 /arch/arm/mach-s5pc100/include
parent23686a07b6222d5c40ea403705325e49d360603e (diff)
ARM: S5PC100: use common plat-s5p external interrupt code
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5pc100/include')
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h33
3 files changed, 28 insertions, 18 deletions
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 29a8a12d9b4f..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
146/* define the number of gpios we need to the one after the MP04() range */ 146/* define the number of gpios we need to the one after the MP04() range */
147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) 147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
148 148
149#define EINT_MODE S3C_GPIO_SFN(0x2)
150
151#define EINT_GPIO_0(x) S5PC100_GPH0(x)
152#define EINT_GPIO_1(x) S5PC100_GPH1(x)
153#define EINT_GPIO_2(x) S5PC100_GPH2(x)
154#define EINT_GPIO_3(x) S5PC100_GPH3(x)
155
149#include <asm-generic/gpio.h> 156#include <asm-generic/gpio.h>
150 157
151#endif /* __ASM_ARCH_GPIO_H */ 158#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 84c74acaa63a..28aa551dc3a8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,10 +97,8 @@
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31) 97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31) 98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99 99
100#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) 100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101 101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \
103 (S5P_IRQ_EINT_BASE + (x)-16))
104 102
105#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) 103#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
106#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) 104#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index cd6200adabce..dd6295e1251d 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -47,24 +47,29 @@
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) 47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) 48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) 49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
51 50
52#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) 51#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
53#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) 52#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
54 53
55/* PDNEN */ 54#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
56#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) 55#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
57#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
58#define S5PC100_PDNEN_POWERDOWN (1 << 0)
59#define S5PC100_PDNEN_NORMAL (0 << 0)
60 56
61/* Common part */ 57#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
62/* External interrupt base is same at both s5pc100 and s5pc110 */ 58#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
63#define S5P_EINT_BASE (S5PC100_EINT_BASE)
64 59
65#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 60#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
66#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 61#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
67#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 62
63#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
64
65#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
66
67/* values for S5P_EXTINT0 */
68#define S5P_EXTINT_LOWLEV (0x00)
69#define S5P_EXTINT_HILEV (0x01)
70#define S5P_EXTINT_FALLEDGE (0x02)
71#define S5P_EXTINT_RISEEDGE (0x03)
72#define S5P_EXTINT_BOTHEDGE (0x04)
68 73
69#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ 74#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
70 75