ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names

Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
[kgene.kim@samsung.com: fixed trailing whitespace]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 78 insertions, 48 deletions

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2addd988141c..415c5406b17c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -243,24 +243,6 @@ static struct clk init_clocks[] = {
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
-        }, {
                 .name           = "otg",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -310,6 +292,29 @@ static struct clk init_clocks[] = {
         }
 };
 
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
+};
 
 static struct clk clk_fout_apll = {
         .name           = "fout_apll",
@@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                         .name           = "usb-bus-host",
                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
                         .enable         = s3c64xx_sclk_ctrl,
@@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = {
         .sources        = &clkset_uart,
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = {
 
 static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uclk,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+};
+
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
 };
 
 static struct clk_lookup s3c64xx_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+                s3c_disable_clocks(clk_cdev[cnt], 1);
+
         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)