[ARM] pxa: move AC97 register definitions into dedicated regs-ac97.h

The optimal change would be to move the AC97 register definitions into the AC97 driver, unfortunately, the registers are shared between several files. Move them into a dedicated regs-ac97.h first. Signed-off-by: Eric Miao <eric.miao@marvell.com>
author: Eric Miao <eric.miao@marvell.com> 2008-11-28 01:19:33 -0500
committer: Eric Miao <eric.miao@marvell.com> 2008-12-02 01:42:39 -0500
commit: 1f017a9964c5b3b9581d3a5732110cb1e0444281 (patch)
tree: a710b14fe62ab2d49cfec9036272cfe4a276c614 /arch/arm/mach-pxa/include/mach/regs-ac97.h
parent: 02f652626a8f23e513877cb751c8ea533739c28f (diff)
1 files changed, 99 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
new file mode 100644
index 000000000000..e41b9d202b8c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H
+/*
+ * AC97 Controller registers
+ */
+#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
+#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define PICR            __REG(0x40500004)  /* PCM In Control Register */
+#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
+#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define GCR             __REG(0x4050000C)  /* Global Control Register */
+#ifdef CONFIG_PXA3xx
+#define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
+#endif
+#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
+#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
+#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
+#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
+#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
+#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
+#define POSR_FIFOE      (1 << 4)        /* FIFO error */
+#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define PISR            __REG(0x40500014)  /* PCM In Status Register */
+#define PISR_FIFOE      (1 << 4)        /* FIFO error */
+#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
+#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define GSR             __REG(0x4050001C)  /* Global Status Register */
+#define GSR_CDONE       (1 << 19)       /* Command Done */
+#define GSR_SDONE       (1 << 18)       /* Status Done */
+#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
+#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
+#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
+#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
+#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
+#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
+#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
+#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
+#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
+#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
+#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
+#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
+#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
+#define CAR             __REG(0x40500020)  /* CODEC Access Register */
+#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
+#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
+#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
+#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
+#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MICR            __REG(0x40500108)  /* Modem In Control Register */
+#define MICR_FEIE       (1 << 3)        /* FIFO Error */
+#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MISR            __REG(0x40500118)  /* Modem In Status Register */
+#define MISR_FIFOE      (1 << 4)        /* FIFO error */
+#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
+#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
+#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
+#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
+#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
+#endif /* __ASM_ARCH_REGS_AC97_H */
author	Eric Miao <eric.miao@marvell.com>	2008-11-28 01:19:33 -0500
committer	Eric Miao <eric.miao@marvell.com>	2008-12-02 01:42:39 -0500
commit	1f017a9964c5b3b9581d3a5732110cb1e0444281 (patch)
tree	a710b14fe62ab2d49cfec9036272cfe4a276c614 /arch/arm/mach-pxa/include/mach/regs-ac97.h
parent	02f652626a8f23e513877cb751c8ea533739c28f (diff)

diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 000000000000..e41b9d202b8c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
	1	#ifndef __ASM_ARCH_REGS_AC97_H
	2	#define __ASM_ARCH_REGS_AC97_H
	3
	4	/*
	5	* AC97 Controller registers
	6	*/
	7
	8	#define POCR __REG(0x40500000) /* PCM Out Control Register */
	9	#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
	10	#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
	11
	12	#define PICR __REG(0x40500004) /* PCM In Control Register */
	13	#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
	14	#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
	15
	16	#define MCCR __REG(0x40500008) /* Mic In Control Register */
	17	#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
	18	#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
	19
	20	#define GCR __REG(0x4050000C) /* Global Control Register */
	21	#ifdef CONFIG_PXA3xx
	22	#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
	23	#endif
	24	#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
	25	#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
	26	#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
	27	#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
	28	#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
	29	#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
	30	#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
	31	#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
	32	#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
	33	#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
	34	#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
	35
	36	#define POSR __REG(0x40500010) /* PCM Out Status Register */
	37	#define POSR_FIFOE (1 << 4) /* FIFO error */
	38	#define POSR_FSR (1 << 2) /* FIFO Service Request */
	39
	40	#define PISR __REG(0x40500014) /* PCM In Status Register */
	41	#define PISR_FIFOE (1 << 4) /* FIFO error */
	42	#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
	43	#define PISR_FSR (1 << 2) /* FIFO Service Request */
	44
	45	#define MCSR __REG(0x40500018) /* Mic In Status Register */
	46	#define MCSR_FIFOE (1 << 4) /* FIFO error */
	47	#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
	48	#define MCSR_FSR (1 << 2) /* FIFO Service Request */
	49
	50	#define GSR __REG(0x4050001C) /* Global Status Register */
	51	#define GSR_CDONE (1 << 19) /* Command Done */
	52	#define GSR_SDONE (1 << 18) /* Status Done */
	53	#define GSR_RDCS (1 << 15) /* Read Completion Status */
	54	#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
	55	#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
	56	#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
	57	#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
	58	#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
	59	#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
	60	#define GSR_PCR (1 << 8) /* Primary Codec Ready */
	61	#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
	62	#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
	63	#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
	64	#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
	65	#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
	66	#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
	67	#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
	68
	69	#define CAR __REG(0x40500020) /* CODEC Access Register */
	70	#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
	71
	72	#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
	73	#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
	74
	75	#define MOCR __REG(0x40500100) /* Modem Out Control Register */
	76	#define MOCR_FEIE (1 << 3) /* FIFO Error */
	77	#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
	78
	79	#define MICR __REG(0x40500108) /* Modem In Control Register */
	80	#define MICR_FEIE (1 << 3) /* FIFO Error */
	81	#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
	82
	83	#define MOSR __REG(0x40500110) /* Modem Out Status Register */
	84	#define MOSR_FIFOE (1 << 4) /* FIFO error */
	85	#define MOSR_FSR (1 << 2) /* FIFO Service Request */
	86
	87	#define MISR __REG(0x40500118) /* Modem In Status Register */
	88	#define MISR_FIFOE (1 << 4) /* FIFO error */
	89	#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
	90	#define MISR_FSR (1 << 2) /* FIFO Service Request */
	91
	92	#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
	93
	94	#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
	95	#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
	96	#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
	97	#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
	98
	99	#endif /* __ASM_ARCH_REGS_AC97_H */