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authorLennert Buytenhek <buytenh@wantstofly.org>2008-05-28 10:43:48 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 16:44:57 -0400
commit79e90dd5aa95adfdc3117db8a559da3d0195ba58 (patch)
treebe2a760b39e8f295aca136da03c05490c77a0b48 /arch/arm/mach-orion5x/pci.c
parent0e3bc0503f7e7b5b0bd4416f43eeeca1b661e66e (diff)
[ARM] Orion: nuke orion5x_{read,write}
Nuke the Orion-specific orion5x_{read,write} wrappers. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/mach-orion5x/pci.c')
-rw-r--r--arch/arm/mach-orion5x/pci.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 275a50046c1f..025ef63b1ddb 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -268,7 +268,7 @@ static DEFINE_SPINLOCK(orion5x_pci_lock);
268 268
269static int orion5x_pci_local_bus_nr(void) 269static int orion5x_pci_local_bus_nr(void)
270{ 270{
271 u32 conf = orion5x_read(PCI_P2P_CONF); 271 u32 conf = readl(PCI_P2P_CONF);
272 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 272 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
273} 273}
274 274
@@ -278,11 +278,11 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
278 unsigned long flags; 278 unsigned long flags;
279 spin_lock_irqsave(&orion5x_pci_lock, flags); 279 spin_lock_irqsave(&orion5x_pci_lock, flags);
280 280
281 orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | 281 writel(PCI_CONF_BUS(bus) |
282 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 282 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
283 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); 283 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
284 284
285 *val = orion5x_read(PCI_CONF_DATA); 285 *val = readl(PCI_CONF_DATA);
286 286
287 if (size == 1) 287 if (size == 1)
288 *val = (*val >> (8*(where & 0x3))) & 0xff; 288 *val = (*val >> (8*(where & 0x3))) & 0xff;
@@ -302,9 +302,9 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
302 302
303 spin_lock_irqsave(&orion5x_pci_lock, flags); 303 spin_lock_irqsave(&orion5x_pci_lock, flags);
304 304
305 orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | 305 writel(PCI_CONF_BUS(bus) |
306 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 306 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
307 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); 307 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
308 308
309 if (size == 4) { 309 if (size == 4) {
310 __raw_writel(val, PCI_CONF_DATA); 310 __raw_writel(val, PCI_CONF_DATA);
@@ -355,9 +355,9 @@ static struct pci_ops pci_ops = {
355 355
356static void __init orion5x_pci_set_bus_nr(int nr) 356static void __init orion5x_pci_set_bus_nr(int nr)
357{ 357{
358 u32 p2p = orion5x_read(PCI_P2P_CONF); 358 u32 p2p = readl(PCI_P2P_CONF);
359 359
360 if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { 360 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
361 /* 361 /*
362 * PCI-X mode 362 * PCI-X mode
363 */ 363 */
@@ -374,7 +374,7 @@ static void __init orion5x_pci_set_bus_nr(int nr)
374 */ 374 */
375 p2p &= ~PCI_P2P_BUS_MASK; 375 p2p &= ~PCI_P2P_BUS_MASK;
376 p2p |= (nr << PCI_P2P_BUS_OFFS); 376 p2p |= (nr << PCI_P2P_BUS_OFFS);
377 orion5x_write(PCI_P2P_CONF, p2p); 377 writel(p2p, PCI_P2P_CONF);
378 } 378 }
379} 379}
380 380
@@ -401,7 +401,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
401 * First, disable windows. 401 * First, disable windows.
402 */ 402 */
403 win_enable = 0xffffffff; 403 win_enable = 0xffffffff;
404 orion5x_write(PCI_BAR_ENABLE, win_enable); 404 writel(win_enable, PCI_BAR_ENABLE);
405 405
406 /* 406 /*
407 * Setup windows for DDR banks. 407 * Setup windows for DDR banks.
@@ -427,10 +427,10 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
427 */ 427 */
428 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 428 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
429 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 429 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
430 orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), 430 writel((cs->size - 1) & 0xfffff000,
431 (cs->size - 1) & 0xfffff000); 431 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
432 orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), 432 writel(cs->base & 0xfffff000,
433 cs->base & 0xfffff000); 433 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
434 434
435 /* 435 /*
436 * Enable decode window for this chip select. 436 * Enable decode window for this chip select.
@@ -441,7 +441,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
441 /* 441 /*
442 * Re-enable decode windows. 442 * Re-enable decode windows.
443 */ 443 */
444 orion5x_write(PCI_BAR_ENABLE, win_enable); 444 writel(win_enable, PCI_BAR_ENABLE);
445 445
446 /* 446 /*
447 * Disable automatic update of address remaping when writing to BARs. 447 * Disable automatic update of address remaping when writing to BARs.