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authorPaul Walmsley <paul@pwsan.com>2012-09-10 16:08:43 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:18:51 -0500
commitf51e0f9862ccf8be71219763d51e7617b95faa10 (patch)
treef02549b8b3211da18a3d82f8f9e74433785770eb /arch/arm/mach-omap2
parentd037e100d138fb522ed0ea3e3a915bd8e0e36f63 (diff)
ARM: OMAP2xxx: clock: drop obsolete clock data
Drop the now-obsolete OMAP2420/2430 original OMAP clock data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c1962
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2061
2 files changed, 0 insertions, 4023 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
deleted file mode 100644
index ec6d53965753..000000000000
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ /dev/null
@@ -1,1962 +0,0 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/list.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "clock.h"
24#include "clock2xxx.h"
25#include "opp2xxx.h"
26#include "cm2xxx.h"
27#include "prm2xxx_3xxx.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "sdrc.h"
31#include "control.h"
32
33#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
34
35/*
36 * 2420 clock tree.
37 *
38 * NOTE:In many cases here we are assigning a 'default' parent. In
39 * many cases the parent is selectable. The set parent calls will
40 * also switch sources.
41 *
42 * Several sources are given initial rates which may be wrong, this will
43 * be fixed up in the init func.
44 *
45 * Things are broadly separated below by clock domains. It is
46 * noteworthy that most peripherals have dependencies on multiple clock
47 * domains. Many get their interface clocks from the L4 domain, but get
48 * functional clocks from fixed sources or other core domain derived
49 * clocks.
50 */
51
52/* Base external input clocks */
53static struct clk func_32k_ck = {
54 .name = "func_32k_ck",
55 .ops = &clkops_null,
56 .rate = 32768,
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63};
64
65/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
66static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
67 .name = "osc_ck",
68 .ops = &clkops_oscck,
69 .clkdm_name = "wkup_clkdm",
70 .recalc = &omap2_osc_clk_recalc,
71};
72
73/* Without modem likely 12MHz, with modem likely 13MHz */
74static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
75 .name = "sys_ck", /* ~ ref_clk also */
76 .ops = &clkops_null,
77 .parent = &osc_ck,
78 .clkdm_name = "wkup_clkdm",
79 .recalc = &omap2xxx_sys_clk_recalc,
80};
81
82static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
83 .name = "alt_ck",
84 .ops = &clkops_null,
85 .rate = 54000000,
86};
87
88/* Optional external clock input for McBSP CLKS */
89static struct clk mcbsp_clks = {
90 .name = "mcbsp_clks",
91 .ops = &clkops_null,
92};
93
94/*
95 * Analog domain root source clocks
96 */
97
98/* dpll_ck, is broken out in to special cases through clksel */
99/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
100 * deal with this
101 */
102
103static struct dpll_data dpll_dd = {
104 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
105 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
106 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
107 .clk_bypass = &sys_ck,
108 .clk_ref = &sys_ck,
109 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
110 .enable_mask = OMAP24XX_EN_DPLL_MASK,
111 .max_multiplier = 1023,
112 .min_divider = 1,
113 .max_divider = 16,
114};
115
116/*
117 * XXX Cannot add round_rate here yet, as this is still a composite clock,
118 * not just a DPLL
119 */
120static struct clk dpll_ck = {
121 .name = "dpll_ck",
122 .ops = &clkops_omap2xxx_dpll_ops,
123 .parent = &sys_ck, /* Can be func_32k also */
124 .init = &omap2xxx_clkt_dpllcore_init,
125 .dpll_data = &dpll_dd,
126 .clkdm_name = "wkup_clkdm",
127 .recalc = &omap2_dpllcore_recalc,
128 .set_rate = &omap2_reprogram_dpllcore,
129};
130
131static struct clk apll96_ck = {
132 .name = "apll96_ck",
133 .ops = &clkops_apll96,
134 .parent = &sys_ck,
135 .rate = 96000000,
136 .flags = ENABLE_ON_INIT,
137 .clkdm_name = "wkup_clkdm",
138 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
139 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
140};
141
142static struct clk apll54_ck = {
143 .name = "apll54_ck",
144 .ops = &clkops_apll54,
145 .parent = &sys_ck,
146 .rate = 54000000,
147 .flags = ENABLE_ON_INIT,
148 .clkdm_name = "wkup_clkdm",
149 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
150 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
151};
152
153/*
154 * PRCM digital base sources
155 */
156
157/* func_54m_ck */
158
159static const struct clksel_rate func_54m_apll54_rates[] = {
160 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
161 { .div = 0 },
162};
163
164static const struct clksel_rate func_54m_alt_rates[] = {
165 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
166 { .div = 0 },
167};
168
169static const struct clksel func_54m_clksel[] = {
170 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
171 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
172 { .parent = NULL },
173};
174
175static struct clk func_54m_ck = {
176 .name = "func_54m_ck",
177 .ops = &clkops_null,
178 .parent = &apll54_ck, /* can also be alt_clk */
179 .init = &omap2_init_clksel_parent,
180 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
181 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
182 .clksel = func_54m_clksel,
183 .recalc = &omap2_clksel_recalc,
184};
185
186static struct clk core_ck = {
187 .name = "core_ck",
188 .ops = &clkops_null,
189 .parent = &dpll_ck, /* can also be 32k */
190 .clkdm_name = "wkup_clkdm",
191 .recalc = &followparent_recalc,
192};
193
194static struct clk func_96m_ck = {
195 .name = "func_96m_ck",
196 .ops = &clkops_null,
197 .parent = &apll96_ck,
198 .clkdm_name = "wkup_clkdm",
199 .recalc = &followparent_recalc,
200};
201
202/* func_48m_ck */
203
204static const struct clksel_rate func_48m_apll96_rates[] = {
205 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
206 { .div = 0 },
207};
208
209static const struct clksel_rate func_48m_alt_rates[] = {
210 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
211 { .div = 0 },
212};
213
214static const struct clksel func_48m_clksel[] = {
215 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
216 { .parent = &alt_ck, .rates = func_48m_alt_rates },
217 { .parent = NULL }
218};
219
220static struct clk func_48m_ck = {
221 .name = "func_48m_ck",
222 .ops = &clkops_null,
223 .parent = &apll96_ck, /* 96M or Alt */
224 .clkdm_name = "wkup_clkdm",
225 .init = &omap2_init_clksel_parent,
226 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
227 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
228 .clksel = func_48m_clksel,
229 .recalc = &omap2_clksel_recalc,
230 .round_rate = &omap2_clksel_round_rate,
231 .set_rate = &omap2_clksel_set_rate
232};
233
234static struct clk func_12m_ck = {
235 .name = "func_12m_ck",
236 .ops = &clkops_null,
237 .parent = &func_48m_ck,
238 .fixed_div = 4,
239 .recalc = &omap_fixed_divisor_recalc,
240};
241
242/* Secure timer, only available in secure mode */
243static struct clk wdt1_osc_ck = {
244 .name = "ck_wdt1_osc",
245 .ops = &clkops_null, /* RMK: missing? */
246 .parent = &osc_ck,
247 .recalc = &followparent_recalc,
248};
249
250/*
251 * The common_clkout* clksel_rate structs are common to
252 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
253 * sys_clkout2_* are 2420-only, so the
254 * clksel_rate flags fields are inaccurate for those clocks. This is
255 * harmless since access to those clocks are gated by the struct clk
256 * flags fields, which mark them as 2420-only.
257 */
258static const struct clksel_rate common_clkout_src_core_rates[] = {
259 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
260 { .div = 0 }
261};
262
263static const struct clksel_rate common_clkout_src_sys_rates[] = {
264 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
265 { .div = 0 }
266};
267
268static const struct clksel_rate common_clkout_src_96m_rates[] = {
269 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
270 { .div = 0 }
271};
272
273static const struct clksel_rate common_clkout_src_54m_rates[] = {
274 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
275 { .div = 0 }
276};
277
278static const struct clksel common_clkout_src_clksel[] = {
279 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
280 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
281 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
282 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
283 { .parent = NULL }
284};
285
286static struct clk sys_clkout_src = {
287 .name = "sys_clkout_src",
288 .ops = &clkops_omap2_dflt,
289 .parent = &func_54m_ck,
290 .clkdm_name = "wkup_clkdm",
291 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
292 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
293 .init = &omap2_init_clksel_parent,
294 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
295 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
296 .clksel = common_clkout_src_clksel,
297 .recalc = &omap2_clksel_recalc,
298 .round_rate = &omap2_clksel_round_rate,
299 .set_rate = &omap2_clksel_set_rate
300};
301
302static const struct clksel_rate common_clkout_rates[] = {
303 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
304 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
305 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
306 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
307 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
308 { .div = 0 },
309};
310
311static const struct clksel sys_clkout_clksel[] = {
312 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
313 { .parent = NULL }
314};
315
316static struct clk sys_clkout = {
317 .name = "sys_clkout",
318 .ops = &clkops_null,
319 .parent = &sys_clkout_src,
320 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
321 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
322 .clksel = sys_clkout_clksel,
323 .recalc = &omap2_clksel_recalc,
324 .round_rate = &omap2_clksel_round_rate,
325 .set_rate = &omap2_clksel_set_rate
326};
327
328/* In 2430, new in 2420 ES2 */
329static struct clk sys_clkout2_src = {
330 .name = "sys_clkout2_src",
331 .ops = &clkops_omap2_dflt,
332 .parent = &func_54m_ck,
333 .clkdm_name = "wkup_clkdm",
334 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
335 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
336 .init = &omap2_init_clksel_parent,
337 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
338 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
339 .clksel = common_clkout_src_clksel,
340 .recalc = &omap2_clksel_recalc,
341 .round_rate = &omap2_clksel_round_rate,
342 .set_rate = &omap2_clksel_set_rate
343};
344
345static const struct clksel sys_clkout2_clksel[] = {
346 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
347 { .parent = NULL }
348};
349
350/* In 2430, new in 2420 ES2 */
351static struct clk sys_clkout2 = {
352 .name = "sys_clkout2",
353 .ops = &clkops_null,
354 .parent = &sys_clkout2_src,
355 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
356 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
357 .clksel = sys_clkout2_clksel,
358 .recalc = &omap2_clksel_recalc,
359 .round_rate = &omap2_clksel_round_rate,
360 .set_rate = &omap2_clksel_set_rate
361};
362
363static struct clk emul_ck = {
364 .name = "emul_ck",
365 .ops = &clkops_omap2_dflt,
366 .parent = &func_54m_ck,
367 .clkdm_name = "wkup_clkdm",
368 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
369 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
370 .recalc = &followparent_recalc,
371
372};
373
374/*
375 * MPU clock domain
376 * Clocks:
377 * MPU_FCLK, MPU_ICLK
378 * INT_M_FCLK, INT_M_I_CLK
379 *
380 * - Individual clocks are hardware managed.
381 * - Base divider comes from: CM_CLKSEL_MPU
382 *
383 */
384static const struct clksel_rate mpu_core_rates[] = {
385 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
386 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
387 { .div = 4, .val = 4, .flags = RATE_IN_242X },
388 { .div = 6, .val = 6, .flags = RATE_IN_242X },
389 { .div = 8, .val = 8, .flags = RATE_IN_242X },
390 { .div = 0 },
391};
392
393static const struct clksel mpu_clksel[] = {
394 { .parent = &core_ck, .rates = mpu_core_rates },
395 { .parent = NULL }
396};
397
398static struct clk mpu_ck = { /* Control cpu */
399 .name = "mpu_ck",
400 .ops = &clkops_null,
401 .parent = &core_ck,
402 .init = &omap2_init_clksel_parent,
403 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
404 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
405 .clksel = mpu_clksel,
406 .recalc = &omap2_clksel_recalc,
407};
408
409/*
410 * DSP (2420-UMA+IVA1) clock domain
411 * Clocks:
412 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
413 *
414 * Won't be too specific here. The core clock comes into this block
415 * it is divided then tee'ed. One branch goes directly to xyz enable
416 * controls. The other branch gets further divided by 2 then possibly
417 * routed into a synchronizer and out of clocks abc.
418 */
419static const struct clksel_rate dsp_fck_core_rates[] = {
420 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
421 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
422 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
423 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
424 { .div = 6, .val = 6, .flags = RATE_IN_242X },
425 { .div = 8, .val = 8, .flags = RATE_IN_242X },
426 { .div = 12, .val = 12, .flags = RATE_IN_242X },
427 { .div = 0 },
428};
429
430static const struct clksel dsp_fck_clksel[] = {
431 { .parent = &core_ck, .rates = dsp_fck_core_rates },
432 { .parent = NULL }
433};
434
435static struct clk dsp_fck = {
436 .name = "dsp_fck",
437 .ops = &clkops_omap2_dflt_wait,
438 .parent = &core_ck,
439 .clkdm_name = "dsp_clkdm",
440 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
441 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
442 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
443 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
444 .clksel = dsp_fck_clksel,
445 .recalc = &omap2_clksel_recalc,
446};
447
448static const struct clksel dsp_ick_clksel[] = {
449 { .parent = &dsp_fck, .rates = dsp_ick_rates },
450 { .parent = NULL }
451};
452
453static struct clk dsp_ick = {
454 .name = "dsp_ick", /* apparently ipi and isp */
455 .ops = &clkops_omap2_iclk_dflt_wait,
456 .parent = &dsp_fck,
457 .clkdm_name = "dsp_clkdm",
458 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
459 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
460 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
461 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
462 .clksel = dsp_ick_clksel,
463 .recalc = &omap2_clksel_recalc,
464};
465
466/*
467 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
468 * the C54x, but which is contained in the DSP powerdomain. Does not
469 * exist on later OMAPs.
470 */
471static struct clk iva1_ifck = {
472 .name = "iva1_ifck",
473 .ops = &clkops_omap2_dflt_wait,
474 .parent = &core_ck,
475 .clkdm_name = "iva1_clkdm",
476 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
477 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
478 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
479 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
480 .clksel = dsp_fck_clksel,
481 .recalc = &omap2_clksel_recalc,
482};
483
484/* IVA1 mpu/int/i/f clocks are /2 of parent */
485static struct clk iva1_mpu_int_ifck = {
486 .name = "iva1_mpu_int_ifck",
487 .ops = &clkops_omap2_dflt_wait,
488 .parent = &iva1_ifck,
489 .clkdm_name = "iva1_clkdm",
490 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
491 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
492 .fixed_div = 2,
493 .recalc = &omap_fixed_divisor_recalc,
494};
495
496/*
497 * L3 clock domain
498 * L3 clocks are used for both interface and functional clocks to
499 * multiple entities. Some of these clocks are completely managed
500 * by hardware, and some others allow software control. Hardware
501 * managed ones general are based on directly CLK_REQ signals and
502 * various auto idle settings. The functional spec sets many of these
503 * as 'tie-high' for their enables.
504 *
505 * I-CLOCKS:
506 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
507 * CAM, HS-USB.
508 * F-CLOCK
509 * SSI.
510 *
511 * GPMC memories and SDRC have timing and clock sensitive registers which
512 * may very well need notification when the clock changes. Currently for low
513 * operating points, these are taken care of in sleep.S.
514 */
515static const struct clksel_rate core_l3_core_rates[] = {
516 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
517 { .div = 2, .val = 2, .flags = RATE_IN_242X },
518 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
519 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
520 { .div = 8, .val = 8, .flags = RATE_IN_242X },
521 { .div = 12, .val = 12, .flags = RATE_IN_242X },
522 { .div = 16, .val = 16, .flags = RATE_IN_242X },
523 { .div = 0 }
524};
525
526static const struct clksel core_l3_clksel[] = {
527 { .parent = &core_ck, .rates = core_l3_core_rates },
528 { .parent = NULL }
529};
530
531static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
532 .name = "core_l3_ck",
533 .ops = &clkops_null,
534 .parent = &core_ck,
535 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
536 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
537 .clksel = core_l3_clksel,
538 .recalc = &omap2_clksel_recalc,
539};
540
541/* usb_l4_ick */
542static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
543 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
544 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
545 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
546 { .div = 0 }
547};
548
549static const struct clksel usb_l4_ick_clksel[] = {
550 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
551 { .parent = NULL },
552};
553
554/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
555static struct clk usb_l4_ick = { /* FS-USB interface clock */
556 .name = "usb_l4_ick",
557 .ops = &clkops_omap2_iclk_dflt_wait,
558 .parent = &core_l3_ck,
559 .clkdm_name = "core_l4_clkdm",
560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
561 .enable_bit = OMAP24XX_EN_USB_SHIFT,
562 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
563 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
564 .clksel = usb_l4_ick_clksel,
565 .recalc = &omap2_clksel_recalc,
566};
567
568/*
569 * L4 clock management domain
570 *
571 * This domain contains lots of interface clocks from the L4 interface, some
572 * functional clocks. Fixed APLL functional source clocks are managed in
573 * this domain.
574 */
575static const struct clksel_rate l4_core_l3_rates[] = {
576 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
577 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
578 { .div = 0 }
579};
580
581static const struct clksel l4_clksel[] = {
582 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
583 { .parent = NULL }
584};
585
586static struct clk l4_ck = { /* used both as an ick and fck */
587 .name = "l4_ck",
588 .ops = &clkops_null,
589 .parent = &core_l3_ck,
590 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
591 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
592 .clksel = l4_clksel,
593 .recalc = &omap2_clksel_recalc,
594};
595
596/*
597 * SSI is in L3 management domain, its direct parent is core not l3,
598 * many core power domain entities are grouped into the L3 clock
599 * domain.
600 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
601 *
602 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
603 */
604static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
605 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
606 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
607 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
608 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
609 { .div = 6, .val = 6, .flags = RATE_IN_242X },
610 { .div = 8, .val = 8, .flags = RATE_IN_242X },
611 { .div = 0 }
612};
613
614static const struct clksel ssi_ssr_sst_fck_clksel[] = {
615 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
616 { .parent = NULL }
617};
618
619static struct clk ssi_ssr_sst_fck = {
620 .name = "ssi_fck",
621 .ops = &clkops_omap2_dflt_wait,
622 .parent = &core_ck,
623 .clkdm_name = "core_l3_clkdm",
624 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
625 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
626 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
627 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
628 .clksel = ssi_ssr_sst_fck_clksel,
629 .recalc = &omap2_clksel_recalc,
630};
631
632/*
633 * Presumably this is the same as SSI_ICLK.
634 * TRM contradicts itself on what clockdomain SSI_ICLK is in
635 */
636static struct clk ssi_l4_ick = {
637 .name = "ssi_l4_ick",
638 .ops = &clkops_omap2_iclk_dflt_wait,
639 .parent = &l4_ck,
640 .clkdm_name = "core_l4_clkdm",
641 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
642 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
643 .recalc = &followparent_recalc,
644};
645
646
647/*
648 * GFX clock domain
649 * Clocks:
650 * GFX_FCLK, GFX_ICLK
651 * GFX_CG1(2d), GFX_CG2(3d)
652 *
653 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
654 * The 2d and 3d clocks run at a hardware determined
655 * divided value of fclk.
656 *
657 */
658
659/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
660static const struct clksel gfx_fck_clksel[] = {
661 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
662 { .parent = NULL },
663};
664
665static struct clk gfx_3d_fck = {
666 .name = "gfx_3d_fck",
667 .ops = &clkops_omap2_dflt_wait,
668 .parent = &core_l3_ck,
669 .clkdm_name = "gfx_clkdm",
670 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
671 .enable_bit = OMAP24XX_EN_3D_SHIFT,
672 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
673 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
674 .clksel = gfx_fck_clksel,
675 .recalc = &omap2_clksel_recalc,
676 .round_rate = &omap2_clksel_round_rate,
677 .set_rate = &omap2_clksel_set_rate
678};
679
680static struct clk gfx_2d_fck = {
681 .name = "gfx_2d_fck",
682 .ops = &clkops_omap2_dflt_wait,
683 .parent = &core_l3_ck,
684 .clkdm_name = "gfx_clkdm",
685 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
686 .enable_bit = OMAP24XX_EN_2D_SHIFT,
687 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
688 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
689 .clksel = gfx_fck_clksel,
690 .recalc = &omap2_clksel_recalc,
691};
692
693/* This interface clock does not have a CM_AUTOIDLE bit */
694static struct clk gfx_ick = {
695 .name = "gfx_ick", /* From l3 */
696 .ops = &clkops_omap2_dflt_wait,
697 .parent = &core_l3_ck,
698 .clkdm_name = "gfx_clkdm",
699 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
700 .enable_bit = OMAP_EN_GFX_SHIFT,
701 .recalc = &followparent_recalc,
702};
703
704/*
705 * DSS clock domain
706 * CLOCKs:
707 * DSS_L4_ICLK, DSS_L3_ICLK,
708 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
709 *
710 * DSS is both initiator and target.
711 */
712/* XXX Add RATE_NOT_VALIDATED */
713
714static const struct clksel_rate dss1_fck_sys_rates[] = {
715 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
716 { .div = 0 }
717};
718
719static const struct clksel_rate dss1_fck_core_rates[] = {
720 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
721 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
722 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
723 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
724 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
725 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
726 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
727 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
728 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
729 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
730 { .div = 0 }
731};
732
733static const struct clksel dss1_fck_clksel[] = {
734 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
735 { .parent = &core_ck, .rates = dss1_fck_core_rates },
736 { .parent = NULL },
737};
738
739static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
740 .name = "dss_ick",
741 .ops = &clkops_omap2_iclk_dflt,
742 .parent = &l4_ck, /* really both l3 and l4 */
743 .clkdm_name = "dss_clkdm",
744 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
745 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
746 .recalc = &followparent_recalc,
747};
748
749static struct clk dss1_fck = {
750 .name = "dss1_fck",
751 .ops = &clkops_omap2_dflt,
752 .parent = &core_ck, /* Core or sys */
753 .clkdm_name = "dss_clkdm",
754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
755 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
756 .init = &omap2_init_clksel_parent,
757 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
758 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
759 .clksel = dss1_fck_clksel,
760 .recalc = &omap2_clksel_recalc,
761};
762
763static const struct clksel_rate dss2_fck_sys_rates[] = {
764 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
765 { .div = 0 }
766};
767
768static const struct clksel_rate dss2_fck_48m_rates[] = {
769 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
770 { .div = 0 }
771};
772
773static const struct clksel dss2_fck_clksel[] = {
774 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
775 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
776 { .parent = NULL }
777};
778
779static struct clk dss2_fck = { /* Alt clk used in power management */
780 .name = "dss2_fck",
781 .ops = &clkops_omap2_dflt,
782 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
783 .clkdm_name = "dss_clkdm",
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
785 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
786 .init = &omap2_init_clksel_parent,
787 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
788 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
789 .clksel = dss2_fck_clksel,
790 .recalc = &omap2_clksel_recalc,
791};
792
793static struct clk dss_54m_fck = { /* Alt clk used in power management */
794 .name = "dss_54m_fck", /* 54m tv clk */
795 .ops = &clkops_omap2_dflt_wait,
796 .parent = &func_54m_ck,
797 .clkdm_name = "dss_clkdm",
798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
799 .enable_bit = OMAP24XX_EN_TV_SHIFT,
800 .recalc = &followparent_recalc,
801};
802
803static struct clk wu_l4_ick = {
804 .name = "wu_l4_ick",
805 .ops = &clkops_null,
806 .parent = &sys_ck,
807 .clkdm_name = "wkup_clkdm",
808 .recalc = &followparent_recalc,
809};
810
811/*
812 * CORE power domain ICLK & FCLK defines.
813 * Many of the these can have more than one possible parent. Entries
814 * here will likely have an L4 interface parent, and may have multiple
815 * functional clock parents.
816 */
817static const struct clksel_rate gpt_alt_rates[] = {
818 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
819 { .div = 0 }
820};
821
822static const struct clksel omap24xx_gpt_clksel[] = {
823 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
824 { .parent = &sys_ck, .rates = gpt_sys_rates },
825 { .parent = &alt_ck, .rates = gpt_alt_rates },
826 { .parent = NULL },
827};
828
829static struct clk gpt1_ick = {
830 .name = "gpt1_ick",
831 .ops = &clkops_omap2_iclk_dflt_wait,
832 .parent = &wu_l4_ick,
833 .clkdm_name = "wkup_clkdm",
834 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
835 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
836 .recalc = &followparent_recalc,
837};
838
839static struct clk gpt1_fck = {
840 .name = "gpt1_fck",
841 .ops = &clkops_omap2_dflt_wait,
842 .parent = &func_32k_ck,
843 .clkdm_name = "core_l4_clkdm",
844 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
845 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
846 .init = &omap2_init_clksel_parent,
847 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
848 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
849 .clksel = omap24xx_gpt_clksel,
850 .recalc = &omap2_clksel_recalc,
851 .round_rate = &omap2_clksel_round_rate,
852 .set_rate = &omap2_clksel_set_rate
853};
854
855static struct clk gpt2_ick = {
856 .name = "gpt2_ick",
857 .ops = &clkops_omap2_iclk_dflt_wait,
858 .parent = &l4_ck,
859 .clkdm_name = "core_l4_clkdm",
860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
861 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
862 .recalc = &followparent_recalc,
863};
864
865static struct clk gpt2_fck = {
866 .name = "gpt2_fck",
867 .ops = &clkops_omap2_dflt_wait,
868 .parent = &func_32k_ck,
869 .clkdm_name = "core_l4_clkdm",
870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
871 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
872 .init = &omap2_init_clksel_parent,
873 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
874 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
875 .clksel = omap24xx_gpt_clksel,
876 .recalc = &omap2_clksel_recalc,
877};
878
879static struct clk gpt3_ick = {
880 .name = "gpt3_ick",
881 .ops = &clkops_omap2_iclk_dflt_wait,
882 .parent = &l4_ck,
883 .clkdm_name = "core_l4_clkdm",
884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
885 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
886 .recalc = &followparent_recalc,
887};
888
889static struct clk gpt3_fck = {
890 .name = "gpt3_fck",
891 .ops = &clkops_omap2_dflt_wait,
892 .parent = &func_32k_ck,
893 .clkdm_name = "core_l4_clkdm",
894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
895 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
896 .init = &omap2_init_clksel_parent,
897 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
898 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
899 .clksel = omap24xx_gpt_clksel,
900 .recalc = &omap2_clksel_recalc,
901};
902
903static struct clk gpt4_ick = {
904 .name = "gpt4_ick",
905 .ops = &clkops_omap2_iclk_dflt_wait,
906 .parent = &l4_ck,
907 .clkdm_name = "core_l4_clkdm",
908 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
909 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
910 .recalc = &followparent_recalc,
911};
912
913static struct clk gpt4_fck = {
914 .name = "gpt4_fck",
915 .ops = &clkops_omap2_dflt_wait,
916 .parent = &func_32k_ck,
917 .clkdm_name = "core_l4_clkdm",
918 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
919 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
920 .init = &omap2_init_clksel_parent,
921 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
922 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
923 .clksel = omap24xx_gpt_clksel,
924 .recalc = &omap2_clksel_recalc,
925};
926
927static struct clk gpt5_ick = {
928 .name = "gpt5_ick",
929 .ops = &clkops_omap2_iclk_dflt_wait,
930 .parent = &l4_ck,
931 .clkdm_name = "core_l4_clkdm",
932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
933 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
934 .recalc = &followparent_recalc,
935};
936
937static struct clk gpt5_fck = {
938 .name = "gpt5_fck",
939 .ops = &clkops_omap2_dflt_wait,
940 .parent = &func_32k_ck,
941 .clkdm_name = "core_l4_clkdm",
942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
943 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
944 .init = &omap2_init_clksel_parent,
945 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
946 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
947 .clksel = omap24xx_gpt_clksel,
948 .recalc = &omap2_clksel_recalc,
949};
950
951static struct clk gpt6_ick = {
952 .name = "gpt6_ick",
953 .ops = &clkops_omap2_iclk_dflt_wait,
954 .parent = &l4_ck,
955 .clkdm_name = "core_l4_clkdm",
956 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
957 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
958 .recalc = &followparent_recalc,
959};
960
961static struct clk gpt6_fck = {
962 .name = "gpt6_fck",
963 .ops = &clkops_omap2_dflt_wait,
964 .parent = &func_32k_ck,
965 .clkdm_name = "core_l4_clkdm",
966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
967 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
968 .init = &omap2_init_clksel_parent,
969 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
970 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
971 .clksel = omap24xx_gpt_clksel,
972 .recalc = &omap2_clksel_recalc,
973};
974
975static struct clk gpt7_ick = {
976 .name = "gpt7_ick",
977 .ops = &clkops_omap2_iclk_dflt_wait,
978 .parent = &l4_ck,
979 .clkdm_name = "core_l4_clkdm",
980 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
981 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
982 .recalc = &followparent_recalc,
983};
984
985static struct clk gpt7_fck = {
986 .name = "gpt7_fck",
987 .ops = &clkops_omap2_dflt_wait,
988 .parent = &func_32k_ck,
989 .clkdm_name = "core_l4_clkdm",
990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
991 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
992 .init = &omap2_init_clksel_parent,
993 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
994 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
995 .clksel = omap24xx_gpt_clksel,
996 .recalc = &omap2_clksel_recalc,
997};
998
999static struct clk gpt8_ick = {
1000 .name = "gpt8_ick",
1001 .ops = &clkops_omap2_iclk_dflt_wait,
1002 .parent = &l4_ck,
1003 .clkdm_name = "core_l4_clkdm",
1004 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1005 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1006 .recalc = &followparent_recalc,
1007};
1008
1009static struct clk gpt8_fck = {
1010 .name = "gpt8_fck",
1011 .ops = &clkops_omap2_dflt_wait,
1012 .parent = &func_32k_ck,
1013 .clkdm_name = "core_l4_clkdm",
1014 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1015 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1016 .init = &omap2_init_clksel_parent,
1017 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1018 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1019 .clksel = omap24xx_gpt_clksel,
1020 .recalc = &omap2_clksel_recalc,
1021};
1022
1023static struct clk gpt9_ick = {
1024 .name = "gpt9_ick",
1025 .ops = &clkops_omap2_iclk_dflt_wait,
1026 .parent = &l4_ck,
1027 .clkdm_name = "core_l4_clkdm",
1028 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1029 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1030 .recalc = &followparent_recalc,
1031};
1032
1033static struct clk gpt9_fck = {
1034 .name = "gpt9_fck",
1035 .ops = &clkops_omap2_dflt_wait,
1036 .parent = &func_32k_ck,
1037 .clkdm_name = "core_l4_clkdm",
1038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1039 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1040 .init = &omap2_init_clksel_parent,
1041 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1042 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1043 .clksel = omap24xx_gpt_clksel,
1044 .recalc = &omap2_clksel_recalc,
1045};
1046
1047static struct clk gpt10_ick = {
1048 .name = "gpt10_ick",
1049 .ops = &clkops_omap2_iclk_dflt_wait,
1050 .parent = &l4_ck,
1051 .clkdm_name = "core_l4_clkdm",
1052 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1053 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1054 .recalc = &followparent_recalc,
1055};
1056
1057static struct clk gpt10_fck = {
1058 .name = "gpt10_fck",
1059 .ops = &clkops_omap2_dflt_wait,
1060 .parent = &func_32k_ck,
1061 .clkdm_name = "core_l4_clkdm",
1062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1063 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1064 .init = &omap2_init_clksel_parent,
1065 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1066 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1067 .clksel = omap24xx_gpt_clksel,
1068 .recalc = &omap2_clksel_recalc,
1069};
1070
1071static struct clk gpt11_ick = {
1072 .name = "gpt11_ick",
1073 .ops = &clkops_omap2_iclk_dflt_wait,
1074 .parent = &l4_ck,
1075 .clkdm_name = "core_l4_clkdm",
1076 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1077 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1078 .recalc = &followparent_recalc,
1079};
1080
1081static struct clk gpt11_fck = {
1082 .name = "gpt11_fck",
1083 .ops = &clkops_omap2_dflt_wait,
1084 .parent = &func_32k_ck,
1085 .clkdm_name = "core_l4_clkdm",
1086 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1087 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1088 .init = &omap2_init_clksel_parent,
1089 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1090 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1091 .clksel = omap24xx_gpt_clksel,
1092 .recalc = &omap2_clksel_recalc,
1093};
1094
1095static struct clk gpt12_ick = {
1096 .name = "gpt12_ick",
1097 .ops = &clkops_omap2_iclk_dflt_wait,
1098 .parent = &l4_ck,
1099 .clkdm_name = "core_l4_clkdm",
1100 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1101 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1102 .recalc = &followparent_recalc,
1103};
1104
1105static struct clk gpt12_fck = {
1106 .name = "gpt12_fck",
1107 .ops = &clkops_omap2_dflt_wait,
1108 .parent = &secure_32k_ck,
1109 .clkdm_name = "core_l4_clkdm",
1110 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1111 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1112 .init = &omap2_init_clksel_parent,
1113 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1114 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1115 .clksel = omap24xx_gpt_clksel,
1116 .recalc = &omap2_clksel_recalc,
1117};
1118
1119static struct clk mcbsp1_ick = {
1120 .name = "mcbsp1_ick",
1121 .ops = &clkops_omap2_iclk_dflt_wait,
1122 .parent = &l4_ck,
1123 .clkdm_name = "core_l4_clkdm",
1124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1125 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1126 .recalc = &followparent_recalc,
1127};
1128
1129static const struct clksel_rate common_mcbsp_96m_rates[] = {
1130 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1131 { .div = 0 }
1132};
1133
1134static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1135 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1136 { .div = 0 }
1137};
1138
1139static const struct clksel mcbsp_fck_clksel[] = {
1140 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1141 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1142 { .parent = NULL }
1143};
1144
1145static struct clk mcbsp1_fck = {
1146 .name = "mcbsp1_fck",
1147 .ops = &clkops_omap2_dflt_wait,
1148 .parent = &func_96m_ck,
1149 .init = &omap2_init_clksel_parent,
1150 .clkdm_name = "core_l4_clkdm",
1151 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1152 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1153 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1154 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1155 .clksel = mcbsp_fck_clksel,
1156 .recalc = &omap2_clksel_recalc,
1157};
1158
1159static struct clk mcbsp2_ick = {
1160 .name = "mcbsp2_ick",
1161 .ops = &clkops_omap2_iclk_dflt_wait,
1162 .parent = &l4_ck,
1163 .clkdm_name = "core_l4_clkdm",
1164 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1165 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1166 .recalc = &followparent_recalc,
1167};
1168
1169static struct clk mcbsp2_fck = {
1170 .name = "mcbsp2_fck",
1171 .ops = &clkops_omap2_dflt_wait,
1172 .parent = &func_96m_ck,
1173 .init = &omap2_init_clksel_parent,
1174 .clkdm_name = "core_l4_clkdm",
1175 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1176 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1177 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1178 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1179 .clksel = mcbsp_fck_clksel,
1180 .recalc = &omap2_clksel_recalc,
1181};
1182
1183static struct clk mcspi1_ick = {
1184 .name = "mcspi1_ick",
1185 .ops = &clkops_omap2_iclk_dflt_wait,
1186 .parent = &l4_ck,
1187 .clkdm_name = "core_l4_clkdm",
1188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1189 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1190 .recalc = &followparent_recalc,
1191};
1192
1193static struct clk mcspi1_fck = {
1194 .name = "mcspi1_fck",
1195 .ops = &clkops_omap2_dflt_wait,
1196 .parent = &func_48m_ck,
1197 .clkdm_name = "core_l4_clkdm",
1198 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1199 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk mcspi2_ick = {
1204 .name = "mcspi2_ick",
1205 .ops = &clkops_omap2_iclk_dflt_wait,
1206 .parent = &l4_ck,
1207 .clkdm_name = "core_l4_clkdm",
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1209 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1210 .recalc = &followparent_recalc,
1211};
1212
1213static struct clk mcspi2_fck = {
1214 .name = "mcspi2_fck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &func_48m_ck,
1217 .clkdm_name = "core_l4_clkdm",
1218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1219 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1220 .recalc = &followparent_recalc,
1221};
1222
1223static struct clk uart1_ick = {
1224 .name = "uart1_ick",
1225 .ops = &clkops_omap2_iclk_dflt_wait,
1226 .parent = &l4_ck,
1227 .clkdm_name = "core_l4_clkdm",
1228 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1229 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1230 .recalc = &followparent_recalc,
1231};
1232
1233static struct clk uart1_fck = {
1234 .name = "uart1_fck",
1235 .ops = &clkops_omap2_dflt_wait,
1236 .parent = &func_48m_ck,
1237 .clkdm_name = "core_l4_clkdm",
1238 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1239 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1240 .recalc = &followparent_recalc,
1241};
1242
1243static struct clk uart2_ick = {
1244 .name = "uart2_ick",
1245 .ops = &clkops_omap2_iclk_dflt_wait,
1246 .parent = &l4_ck,
1247 .clkdm_name = "core_l4_clkdm",
1248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1249 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1250 .recalc = &followparent_recalc,
1251};
1252
1253static struct clk uart2_fck = {
1254 .name = "uart2_fck",
1255 .ops = &clkops_omap2_dflt_wait,
1256 .parent = &func_48m_ck,
1257 .clkdm_name = "core_l4_clkdm",
1258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1259 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1260 .recalc = &followparent_recalc,
1261};
1262
1263static struct clk uart3_ick = {
1264 .name = "uart3_ick",
1265 .ops = &clkops_omap2_iclk_dflt_wait,
1266 .parent = &l4_ck,
1267 .clkdm_name = "core_l4_clkdm",
1268 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1269 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1270 .recalc = &followparent_recalc,
1271};
1272
1273static struct clk uart3_fck = {
1274 .name = "uart3_fck",
1275 .ops = &clkops_omap2_dflt_wait,
1276 .parent = &func_48m_ck,
1277 .clkdm_name = "core_l4_clkdm",
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1279 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1280 .recalc = &followparent_recalc,
1281};
1282
1283static struct clk gpios_ick = {
1284 .name = "gpios_ick",
1285 .ops = &clkops_omap2_iclk_dflt_wait,
1286 .parent = &wu_l4_ick,
1287 .clkdm_name = "wkup_clkdm",
1288 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1289 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1290 .recalc = &followparent_recalc,
1291};
1292
1293static struct clk gpios_fck = {
1294 .name = "gpios_fck",
1295 .ops = &clkops_omap2_dflt_wait,
1296 .parent = &func_32k_ck,
1297 .clkdm_name = "wkup_clkdm",
1298 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1299 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1300 .recalc = &followparent_recalc,
1301};
1302
1303static struct clk mpu_wdt_ick = {
1304 .name = "mpu_wdt_ick",
1305 .ops = &clkops_omap2_iclk_dflt_wait,
1306 .parent = &wu_l4_ick,
1307 .clkdm_name = "wkup_clkdm",
1308 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1309 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1310 .recalc = &followparent_recalc,
1311};
1312
1313static struct clk mpu_wdt_fck = {
1314 .name = "mpu_wdt_fck",
1315 .ops = &clkops_omap2_dflt_wait,
1316 .parent = &func_32k_ck,
1317 .clkdm_name = "wkup_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1320 .recalc = &followparent_recalc,
1321};
1322
1323static struct clk sync_32k_ick = {
1324 .name = "sync_32k_ick",
1325 .ops = &clkops_omap2_iclk_dflt_wait,
1326 .parent = &wu_l4_ick,
1327 .clkdm_name = "wkup_clkdm",
1328 .flags = ENABLE_ON_INIT,
1329 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1330 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1331 .recalc = &followparent_recalc,
1332};
1333
1334static struct clk wdt1_ick = {
1335 .name = "wdt1_ick",
1336 .ops = &clkops_omap2_iclk_dflt_wait,
1337 .parent = &wu_l4_ick,
1338 .clkdm_name = "wkup_clkdm",
1339 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1340 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1341 .recalc = &followparent_recalc,
1342};
1343
1344static struct clk omapctrl_ick = {
1345 .name = "omapctrl_ick",
1346 .ops = &clkops_omap2_iclk_dflt_wait,
1347 .parent = &wu_l4_ick,
1348 .clkdm_name = "wkup_clkdm",
1349 .flags = ENABLE_ON_INIT,
1350 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1351 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1352 .recalc = &followparent_recalc,
1353};
1354
1355static struct clk cam_ick = {
1356 .name = "cam_ick",
1357 .ops = &clkops_omap2_iclk_dflt,
1358 .parent = &l4_ck,
1359 .clkdm_name = "core_l4_clkdm",
1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1361 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1362 .recalc = &followparent_recalc,
1363};
1364
1365/*
1366 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1367 * split into two separate clocks, since the parent clocks are different
1368 * and the clockdomains are also different.
1369 */
1370static struct clk cam_fck = {
1371 .name = "cam_fck",
1372 .ops = &clkops_omap2_dflt,
1373 .parent = &func_96m_ck,
1374 .clkdm_name = "core_l3_clkdm",
1375 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1376 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1377 .recalc = &followparent_recalc,
1378};
1379
1380static struct clk mailboxes_ick = {
1381 .name = "mailboxes_ick",
1382 .ops = &clkops_omap2_iclk_dflt_wait,
1383 .parent = &l4_ck,
1384 .clkdm_name = "core_l4_clkdm",
1385 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1386 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1387 .recalc = &followparent_recalc,
1388};
1389
1390static struct clk wdt4_ick = {
1391 .name = "wdt4_ick",
1392 .ops = &clkops_omap2_iclk_dflt_wait,
1393 .parent = &l4_ck,
1394 .clkdm_name = "core_l4_clkdm",
1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1396 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1397 .recalc = &followparent_recalc,
1398};
1399
1400static struct clk wdt4_fck = {
1401 .name = "wdt4_fck",
1402 .ops = &clkops_omap2_dflt_wait,
1403 .parent = &func_32k_ck,
1404 .clkdm_name = "core_l4_clkdm",
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1407 .recalc = &followparent_recalc,
1408};
1409
1410static struct clk wdt3_ick = {
1411 .name = "wdt3_ick",
1412 .ops = &clkops_omap2_iclk_dflt_wait,
1413 .parent = &l4_ck,
1414 .clkdm_name = "core_l4_clkdm",
1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1416 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1417 .recalc = &followparent_recalc,
1418};
1419
1420static struct clk wdt3_fck = {
1421 .name = "wdt3_fck",
1422 .ops = &clkops_omap2_dflt_wait,
1423 .parent = &func_32k_ck,
1424 .clkdm_name = "core_l4_clkdm",
1425 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1426 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1427 .recalc = &followparent_recalc,
1428};
1429
1430static struct clk mspro_ick = {
1431 .name = "mspro_ick",
1432 .ops = &clkops_omap2_iclk_dflt_wait,
1433 .parent = &l4_ck,
1434 .clkdm_name = "core_l4_clkdm",
1435 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1436 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1437 .recalc = &followparent_recalc,
1438};
1439
1440static struct clk mspro_fck = {
1441 .name = "mspro_fck",
1442 .ops = &clkops_omap2_dflt_wait,
1443 .parent = &func_96m_ck,
1444 .clkdm_name = "core_l4_clkdm",
1445 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1447 .recalc = &followparent_recalc,
1448};
1449
1450static struct clk mmc_ick = {
1451 .name = "mmc_ick",
1452 .ops = &clkops_omap2_iclk_dflt_wait,
1453 .parent = &l4_ck,
1454 .clkdm_name = "core_l4_clkdm",
1455 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1456 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1457 .recalc = &followparent_recalc,
1458};
1459
1460static struct clk mmc_fck = {
1461 .name = "mmc_fck",
1462 .ops = &clkops_omap2_dflt_wait,
1463 .parent = &func_96m_ck,
1464 .clkdm_name = "core_l4_clkdm",
1465 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1467 .recalc = &followparent_recalc,
1468};
1469
1470static struct clk fac_ick = {
1471 .name = "fac_ick",
1472 .ops = &clkops_omap2_iclk_dflt_wait,
1473 .parent = &l4_ck,
1474 .clkdm_name = "core_l4_clkdm",
1475 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1476 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1477 .recalc = &followparent_recalc,
1478};
1479
1480static struct clk fac_fck = {
1481 .name = "fac_fck",
1482 .ops = &clkops_omap2_dflt_wait,
1483 .parent = &func_12m_ck,
1484 .clkdm_name = "core_l4_clkdm",
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1487 .recalc = &followparent_recalc,
1488};
1489
1490static struct clk eac_ick = {
1491 .name = "eac_ick",
1492 .ops = &clkops_omap2_iclk_dflt_wait,
1493 .parent = &l4_ck,
1494 .clkdm_name = "core_l4_clkdm",
1495 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1496 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1497 .recalc = &followparent_recalc,
1498};
1499
1500static struct clk eac_fck = {
1501 .name = "eac_fck",
1502 .ops = &clkops_omap2_dflt_wait,
1503 .parent = &func_96m_ck,
1504 .clkdm_name = "core_l4_clkdm",
1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1507 .recalc = &followparent_recalc,
1508};
1509
1510static struct clk hdq_ick = {
1511 .name = "hdq_ick",
1512 .ops = &clkops_omap2_iclk_dflt_wait,
1513 .parent = &l4_ck,
1514 .clkdm_name = "core_l4_clkdm",
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1516 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1517 .recalc = &followparent_recalc,
1518};
1519
1520static struct clk hdq_fck = {
1521 .name = "hdq_fck",
1522 .ops = &clkops_omap2_dflt_wait,
1523 .parent = &func_12m_ck,
1524 .clkdm_name = "core_l4_clkdm",
1525 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1527 .recalc = &followparent_recalc,
1528};
1529
1530static struct clk i2c2_ick = {
1531 .name = "i2c2_ick",
1532 .ops = &clkops_omap2_iclk_dflt_wait,
1533 .parent = &l4_ck,
1534 .clkdm_name = "core_l4_clkdm",
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1536 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1537 .recalc = &followparent_recalc,
1538};
1539
1540static struct clk i2c2_fck = {
1541 .name = "i2c2_fck",
1542 .ops = &clkops_omap2_dflt_wait,
1543 .parent = &func_12m_ck,
1544 .clkdm_name = "core_l4_clkdm",
1545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1547 .recalc = &followparent_recalc,
1548};
1549
1550static struct clk i2c1_ick = {
1551 .name = "i2c1_ick",
1552 .ops = &clkops_omap2_iclk_dflt_wait,
1553 .parent = &l4_ck,
1554 .clkdm_name = "core_l4_clkdm",
1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1556 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1557 .recalc = &followparent_recalc,
1558};
1559
1560static struct clk i2c1_fck = {
1561 .name = "i2c1_fck",
1562 .ops = &clkops_omap2_dflt_wait,
1563 .parent = &func_12m_ck,
1564 .clkdm_name = "core_l4_clkdm",
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1567 .recalc = &followparent_recalc,
1568};
1569
1570/*
1571 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1572 * accesses derived from this data.
1573 */
1574static struct clk gpmc_fck = {
1575 .name = "gpmc_fck",
1576 .ops = &clkops_omap2_iclk_idle_only,
1577 .parent = &core_l3_ck,
1578 .flags = ENABLE_ON_INIT,
1579 .clkdm_name = "core_l3_clkdm",
1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1581 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1582 .recalc = &followparent_recalc,
1583};
1584
1585static struct clk sdma_fck = {
1586 .name = "sdma_fck",
1587 .ops = &clkops_null, /* RMK: missing? */
1588 .parent = &core_l3_ck,
1589 .clkdm_name = "core_l3_clkdm",
1590 .recalc = &followparent_recalc,
1591};
1592
1593/*
1594 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1595 * accesses derived from this data.
1596 */
1597static struct clk sdma_ick = {
1598 .name = "sdma_ick",
1599 .ops = &clkops_omap2_iclk_idle_only,
1600 .parent = &core_l3_ck,
1601 .clkdm_name = "core_l3_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1603 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1604 .recalc = &followparent_recalc,
1605};
1606
1607/*
1608 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1609 * accesses derived from this data.
1610 */
1611static struct clk sdrc_ick = {
1612 .name = "sdrc_ick",
1613 .ops = &clkops_omap2_iclk_idle_only,
1614 .parent = &core_l3_ck,
1615 .flags = ENABLE_ON_INIT,
1616 .clkdm_name = "core_l3_clkdm",
1617 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1618 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1619 .recalc = &followparent_recalc,
1620};
1621
1622static struct clk vlynq_ick = {
1623 .name = "vlynq_ick",
1624 .ops = &clkops_omap2_iclk_dflt_wait,
1625 .parent = &core_l3_ck,
1626 .clkdm_name = "core_l3_clkdm",
1627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1628 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1629 .recalc = &followparent_recalc,
1630};
1631
1632static const struct clksel_rate vlynq_fck_96m_rates[] = {
1633 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1634 { .div = 0 }
1635};
1636
1637static const struct clksel_rate vlynq_fck_core_rates[] = {
1638 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1639 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1640 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1641 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1642 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1643 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1644 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1645 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1646 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1647 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1648 { .div = 0 }
1649};
1650
1651static const struct clksel vlynq_fck_clksel[] = {
1652 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1653 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1654 { .parent = NULL }
1655};
1656
1657static struct clk vlynq_fck = {
1658 .name = "vlynq_fck",
1659 .ops = &clkops_omap2_dflt_wait,
1660 .parent = &func_96m_ck,
1661 .clkdm_name = "core_l3_clkdm",
1662 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1663 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1666 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1667 .clksel = vlynq_fck_clksel,
1668 .recalc = &omap2_clksel_recalc,
1669};
1670
1671static struct clk des_ick = {
1672 .name = "des_ick",
1673 .ops = &clkops_omap2_iclk_dflt_wait,
1674 .parent = &l4_ck,
1675 .clkdm_name = "core_l4_clkdm",
1676 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1677 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1678 .recalc = &followparent_recalc,
1679};
1680
1681static struct clk sha_ick = {
1682 .name = "sha_ick",
1683 .ops = &clkops_omap2_iclk_dflt_wait,
1684 .parent = &l4_ck,
1685 .clkdm_name = "core_l4_clkdm",
1686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1687 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1688 .recalc = &followparent_recalc,
1689};
1690
1691static struct clk rng_ick = {
1692 .name = "rng_ick",
1693 .ops = &clkops_omap2_iclk_dflt_wait,
1694 .parent = &l4_ck,
1695 .clkdm_name = "core_l4_clkdm",
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1697 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1698 .recalc = &followparent_recalc,
1699};
1700
1701static struct clk aes_ick = {
1702 .name = "aes_ick",
1703 .ops = &clkops_omap2_iclk_dflt_wait,
1704 .parent = &l4_ck,
1705 .clkdm_name = "core_l4_clkdm",
1706 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1707 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1708 .recalc = &followparent_recalc,
1709};
1710
1711static struct clk pka_ick = {
1712 .name = "pka_ick",
1713 .ops = &clkops_omap2_iclk_dflt_wait,
1714 .parent = &l4_ck,
1715 .clkdm_name = "core_l4_clkdm",
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1717 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1718 .recalc = &followparent_recalc,
1719};
1720
1721static struct clk usb_fck = {
1722 .name = "usb_fck",
1723 .ops = &clkops_omap2_dflt_wait,
1724 .parent = &func_48m_ck,
1725 .clkdm_name = "core_l3_clkdm",
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1727 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1728 .recalc = &followparent_recalc,
1729};
1730
1731/*
1732 * This clock is a composite clock which does entire set changes then
1733 * forces a rebalance. It keys on the MPU speed, but it really could
1734 * be any key speed part of a set in the rate table.
1735 *
1736 * to really change a set, you need memory table sets which get changed
1737 * in sram, pre-notifiers & post notifiers, changing the top set, without
1738 * having low level display recalc's won't work... this is why dpm notifiers
1739 * work, isr's off, walk a list of clocks already _off_ and not messing with
1740 * the bus.
1741 *
1742 * This clock should have no parent. It embodies the entire upper level
1743 * active set. A parent will mess up some of the init also.
1744 */
1745static struct clk virt_prcm_set = {
1746 .name = "virt_prcm_set",
1747 .ops = &clkops_null,
1748 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1749 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1750 .set_rate = &omap2_select_table_rate,
1751 .round_rate = &omap2_round_to_table_rate,
1752};
1753
1754
1755/*
1756 * clkdev integration
1757 */
1758
1759static struct omap_clk omap2420_clks[] = {
1760 /* external root sources */
1761 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1762 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1763 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1764 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1765 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1766 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1767 /* internal analog sources */
1768 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1769 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1770 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1771 /* internal prcm root sources */
1772 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1773 CLK(NULL, "core_ck", &core_ck, CK_242X),
1774 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1775 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1776 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1777 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1778 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1779 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1780 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1781 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1782 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1783 /* mpu domain clocks */
1784 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1785 /* dsp domain clocks */
1786 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1787 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1788 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1789 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1790 /* GFX domain clocks */
1791 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1792 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1793 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1794 /* DSS domain clocks */
1795 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1796 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
1797 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1798 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1799 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1800 /* L3 domain clocks */
1801 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1802 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1803 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1804 /* L4 domain clocks */
1805 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1806 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1807 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1808 /* virtual meta-group clock */
1809 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1810 /* general l4 interface ck, multi-parent functional clk */
1811 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1812 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1813 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1814 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1815 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1816 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1817 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1818 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1819 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1820 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1821 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1822 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1823 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1824 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1825 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1826 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1827 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1828 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1829 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1830 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1831 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1832 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1833 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1834 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1835 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1836 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
1837 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1838 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1839 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
1840 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1841 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1842 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
1843 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1844 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1845 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
1846 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1847 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1848 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1849 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1850 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1851 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1852 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1853 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1854 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1855 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1856 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
1857 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1858 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1859 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1860 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1861 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1862 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
1863 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1864 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
1865 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1866 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1867 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1868 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1869 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1870 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1871 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1872 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1873 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
1874 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1875 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
1876 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1877 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1878 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1879 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1880 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1881 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
1882 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1883 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
1884 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1885 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
1886 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1887 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1888 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
1889 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1890 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1891 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1892 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1893 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1894 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1895 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1896 CLK(NULL, "des_ick", &des_ick, CK_242X),
1897 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1898 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1899 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1900 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
1901 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1902 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1903 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1904 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1905 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1906 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1907 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1908 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
1909 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
1910};
1911
1912/*
1913 * init code
1914 */
1915
1916int __init omap2420_clk_init(void)
1917{
1918 struct omap_clk *c;
1919
1920 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1921 cpu_mask = RATE_IN_242X;
1922 rate_table = omap2420_rate_table;
1923
1924 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1925 c++)
1926 clk_preinit(c->lk.clk);
1927
1928 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1929 propagate_rate(&osc_ck);
1930 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1931 propagate_rate(&sys_ck);
1932
1933 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1934 c++) {
1935 clkdev_add(&c->lk);
1936 clk_register(c->lk.clk);
1937 omap2_init_clk_clkdm(c->lk.clk);
1938 }
1939
1940 omap2xxx_clkt_vps_late_init();
1941
1942 /* Disable autoidle on all clocks; let the PM code enable it later */
1943 omap_clk_disable_autoidle_all();
1944
1945 /* XXX Can this be done from the virt_prcm_set clk init function? */
1946 omap2xxx_clkt_vps_check_bootloader_rates();
1947
1948 recalculate_root_clocks();
1949
1950 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1951 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1952 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1953
1954 /*
1955 * Only enable those clocks we will need, let the drivers
1956 * enable other clocks as necessary
1957 */
1958 clk_enable_init_clocks();
1959
1960 return 0;
1961}
1962
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
deleted file mode 100644
index b2d2fb35d519..000000000000
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ /dev/null
@@ -1,2061 +0,0 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include "soc.h"
21#include "iomap.h"
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
33
34/*
35 * 2430 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56};
57
58static struct clk secure_32k_ck = {
59 .name = "secure_32k_ck",
60 .ops = &clkops_null,
61 .rate = 32768,
62};
63
64/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
65static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
66 .name = "osc_ck",
67 .ops = &clkops_oscck,
68 .clkdm_name = "wkup_clkdm",
69 .recalc = &omap2_osc_clk_recalc,
70};
71
72/* Without modem likely 12MHz, with modem likely 13MHz */
73static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
74 .name = "sys_ck", /* ~ ref_clk also */
75 .ops = &clkops_null,
76 .parent = &osc_ck,
77 .clkdm_name = "wkup_clkdm",
78 .recalc = &omap2xxx_sys_clk_recalc,
79};
80
81static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
82 .name = "alt_ck",
83 .ops = &clkops_null,
84 .rate = 54000000,
85};
86
87/* Optional external clock input for McBSP CLKS */
88static struct clk mcbsp_clks = {
89 .name = "mcbsp_clks",
90 .ops = &clkops_null,
91};
92
93/*
94 * Analog domain root source clocks
95 */
96
97/* dpll_ck, is broken out in to special cases through clksel */
98/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
99 * deal with this
100 */
101
102static struct dpll_data dpll_dd = {
103 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
104 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
105 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
106 .clk_bypass = &sys_ck,
107 .clk_ref = &sys_ck,
108 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
109 .enable_mask = OMAP24XX_EN_DPLL_MASK,
110 .max_multiplier = 1023,
111 .min_divider = 1,
112 .max_divider = 16,
113};
114
115/*
116 * XXX Cannot add round_rate here yet, as this is still a composite clock,
117 * not just a DPLL
118 */
119static struct clk dpll_ck = {
120 .name = "dpll_ck",
121 .ops = &clkops_omap2xxx_dpll_ops,
122 .parent = &sys_ck, /* Can be func_32k also */
123 .init = &omap2xxx_clkt_dpllcore_init,
124 .dpll_data = &dpll_dd,
125 .clkdm_name = "wkup_clkdm",
126 .recalc = &omap2_dpllcore_recalc,
127 .set_rate = &omap2_reprogram_dpllcore,
128};
129
130static struct clk apll96_ck = {
131 .name = "apll96_ck",
132 .ops = &clkops_apll96,
133 .parent = &sys_ck,
134 .rate = 96000000,
135 .flags = ENABLE_ON_INIT,
136 .clkdm_name = "wkup_clkdm",
137 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
138 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
139};
140
141static struct clk apll54_ck = {
142 .name = "apll54_ck",
143 .ops = &clkops_apll54,
144 .parent = &sys_ck,
145 .rate = 54000000,
146 .flags = ENABLE_ON_INIT,
147 .clkdm_name = "wkup_clkdm",
148 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
149 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
150};
151
152/*
153 * PRCM digital base sources
154 */
155
156/* func_54m_ck */
157
158static const struct clksel_rate func_54m_apll54_rates[] = {
159 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
160 { .div = 0 },
161};
162
163static const struct clksel_rate func_54m_alt_rates[] = {
164 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
165 { .div = 0 },
166};
167
168static const struct clksel func_54m_clksel[] = {
169 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
170 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
171 { .parent = NULL },
172};
173
174static struct clk func_54m_ck = {
175 .name = "func_54m_ck",
176 .ops = &clkops_null,
177 .parent = &apll54_ck, /* can also be alt_clk */
178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
180 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
181 .clksel = func_54m_clksel,
182 .recalc = &omap2_clksel_recalc,
183};
184
185static struct clk core_ck = {
186 .name = "core_ck",
187 .ops = &clkops_null,
188 .parent = &dpll_ck, /* can also be 32k */
189 .clkdm_name = "wkup_clkdm",
190 .recalc = &followparent_recalc,
191};
192
193/* func_96m_ck */
194static const struct clksel_rate func_96m_apll96_rates[] = {
195 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
196 { .div = 0 },
197};
198
199static const struct clksel_rate func_96m_alt_rates[] = {
200 { .div = 1, .val = 1, .flags = RATE_IN_243X },
201 { .div = 0 },
202};
203
204static const struct clksel func_96m_clksel[] = {
205 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
206 { .parent = &alt_ck, .rates = func_96m_alt_rates },
207 { .parent = NULL }
208};
209
210static struct clk func_96m_ck = {
211 .name = "func_96m_ck",
212 .ops = &clkops_null,
213 .parent = &apll96_ck,
214 .init = &omap2_init_clksel_parent,
215 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
216 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
217 .clksel = func_96m_clksel,
218 .recalc = &omap2_clksel_recalc,
219};
220
221/* func_48m_ck */
222
223static const struct clksel_rate func_48m_apll96_rates[] = {
224 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
225 { .div = 0 },
226};
227
228static const struct clksel_rate func_48m_alt_rates[] = {
229 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
230 { .div = 0 },
231};
232
233static const struct clksel func_48m_clksel[] = {
234 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
235 { .parent = &alt_ck, .rates = func_48m_alt_rates },
236 { .parent = NULL }
237};
238
239static struct clk func_48m_ck = {
240 .name = "func_48m_ck",
241 .ops = &clkops_null,
242 .parent = &apll96_ck, /* 96M or Alt */
243 .clkdm_name = "wkup_clkdm",
244 .init = &omap2_init_clksel_parent,
245 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
246 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
247 .clksel = func_48m_clksel,
248 .recalc = &omap2_clksel_recalc,
249 .round_rate = &omap2_clksel_round_rate,
250 .set_rate = &omap2_clksel_set_rate
251};
252
253static struct clk func_12m_ck = {
254 .name = "func_12m_ck",
255 .ops = &clkops_null,
256 .parent = &func_48m_ck,
257 .fixed_div = 4,
258 .recalc = &omap_fixed_divisor_recalc,
259};
260
261/* Secure timer, only available in secure mode */
262static struct clk wdt1_osc_ck = {
263 .name = "ck_wdt1_osc",
264 .ops = &clkops_null, /* RMK: missing? */
265 .parent = &osc_ck,
266 .recalc = &followparent_recalc,
267};
268
269/*
270 * The common_clkout* clksel_rate structs are common to
271 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
272 * sys_clkout2_* are 2420-only, so the
273 * clksel_rate flags fields are inaccurate for those clocks. This is
274 * harmless since access to those clocks are gated by the struct clk
275 * flags fields, which mark them as 2420-only.
276 */
277static const struct clksel_rate common_clkout_src_core_rates[] = {
278 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
279 { .div = 0 }
280};
281
282static const struct clksel_rate common_clkout_src_sys_rates[] = {
283 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
284 { .div = 0 }
285};
286
287static const struct clksel_rate common_clkout_src_96m_rates[] = {
288 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
289 { .div = 0 }
290};
291
292static const struct clksel_rate common_clkout_src_54m_rates[] = {
293 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
294 { .div = 0 }
295};
296
297static const struct clksel common_clkout_src_clksel[] = {
298 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
299 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
300 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
301 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
302 { .parent = NULL }
303};
304
305static struct clk sys_clkout_src = {
306 .name = "sys_clkout_src",
307 .ops = &clkops_omap2_dflt,
308 .parent = &func_54m_ck,
309 .clkdm_name = "wkup_clkdm",
310 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
311 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
312 .init = &omap2_init_clksel_parent,
313 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
314 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
315 .clksel = common_clkout_src_clksel,
316 .recalc = &omap2_clksel_recalc,
317 .round_rate = &omap2_clksel_round_rate,
318 .set_rate = &omap2_clksel_set_rate
319};
320
321static const struct clksel_rate common_clkout_rates[] = {
322 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
323 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
324 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
325 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
326 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
327 { .div = 0 },
328};
329
330static const struct clksel sys_clkout_clksel[] = {
331 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
332 { .parent = NULL }
333};
334
335static struct clk sys_clkout = {
336 .name = "sys_clkout",
337 .ops = &clkops_null,
338 .parent = &sys_clkout_src,
339 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
340 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
341 .clksel = sys_clkout_clksel,
342 .recalc = &omap2_clksel_recalc,
343 .round_rate = &omap2_clksel_round_rate,
344 .set_rate = &omap2_clksel_set_rate
345};
346
347static struct clk emul_ck = {
348 .name = "emul_ck",
349 .ops = &clkops_omap2_dflt,
350 .parent = &func_54m_ck,
351 .clkdm_name = "wkup_clkdm",
352 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
353 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
354 .recalc = &followparent_recalc,
355
356};
357
358/*
359 * MPU clock domain
360 * Clocks:
361 * MPU_FCLK, MPU_ICLK
362 * INT_M_FCLK, INT_M_I_CLK
363 *
364 * - Individual clocks are hardware managed.
365 * - Base divider comes from: CM_CLKSEL_MPU
366 *
367 */
368static const struct clksel_rate mpu_core_rates[] = {
369 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
370 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
371 { .div = 0 },
372};
373
374static const struct clksel mpu_clksel[] = {
375 { .parent = &core_ck, .rates = mpu_core_rates },
376 { .parent = NULL }
377};
378
379static struct clk mpu_ck = { /* Control cpu */
380 .name = "mpu_ck",
381 .ops = &clkops_null,
382 .parent = &core_ck,
383 .init = &omap2_init_clksel_parent,
384 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
385 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
386 .clksel = mpu_clksel,
387 .recalc = &omap2_clksel_recalc,
388};
389
390/*
391 * DSP (2430-IVA2.1) clock domain
392 * Clocks:
393 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
394 *
395 * Won't be too specific here. The core clock comes into this block
396 * it is divided then tee'ed. One branch goes directly to xyz enable
397 * controls. The other branch gets further divided by 2 then possibly
398 * routed into a synchronizer and out of clocks abc.
399 */
400static const struct clksel_rate dsp_fck_core_rates[] = {
401 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
402 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
403 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
404 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
405 { .div = 0 },
406};
407
408static const struct clksel dsp_fck_clksel[] = {
409 { .parent = &core_ck, .rates = dsp_fck_core_rates },
410 { .parent = NULL }
411};
412
413static struct clk dsp_fck = {
414 .name = "dsp_fck",
415 .ops = &clkops_omap2_dflt_wait,
416 .parent = &core_ck,
417 .clkdm_name = "dsp_clkdm",
418 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
419 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
420 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
421 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
422 .clksel = dsp_fck_clksel,
423 .recalc = &omap2_clksel_recalc,
424};
425
426static const struct clksel dsp_ick_clksel[] = {
427 { .parent = &dsp_fck, .rates = dsp_ick_rates },
428 { .parent = NULL }
429};
430
431/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
432static struct clk iva2_1_ick = {
433 .name = "iva2_1_ick",
434 .ops = &clkops_omap2_dflt_wait,
435 .parent = &dsp_fck,
436 .clkdm_name = "dsp_clkdm",
437 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
438 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
439 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
440 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
441 .clksel = dsp_ick_clksel,
442 .recalc = &omap2_clksel_recalc,
443};
444
445/*
446 * L3 clock domain
447 * L3 clocks are used for both interface and functional clocks to
448 * multiple entities. Some of these clocks are completely managed
449 * by hardware, and some others allow software control. Hardware
450 * managed ones general are based on directly CLK_REQ signals and
451 * various auto idle settings. The functional spec sets many of these
452 * as 'tie-high' for their enables.
453 *
454 * I-CLOCKS:
455 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
456 * CAM, HS-USB.
457 * F-CLOCK
458 * SSI.
459 *
460 * GPMC memories and SDRC have timing and clock sensitive registers which
461 * may very well need notification when the clock changes. Currently for low
462 * operating points, these are taken care of in sleep.S.
463 */
464static const struct clksel_rate core_l3_core_rates[] = {
465 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
466 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
467 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
468 { .div = 0 }
469};
470
471static const struct clksel core_l3_clksel[] = {
472 { .parent = &core_ck, .rates = core_l3_core_rates },
473 { .parent = NULL }
474};
475
476static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
477 .name = "core_l3_ck",
478 .ops = &clkops_null,
479 .parent = &core_ck,
480 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
481 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
482 .clksel = core_l3_clksel,
483 .recalc = &omap2_clksel_recalc,
484};
485
486/* usb_l4_ick */
487static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
488 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
489 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
490 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
491 { .div = 0 }
492};
493
494static const struct clksel usb_l4_ick_clksel[] = {
495 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
496 { .parent = NULL },
497};
498
499/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
500static struct clk usb_l4_ick = { /* FS-USB interface clock */
501 .name = "usb_l4_ick",
502 .ops = &clkops_omap2_iclk_dflt_wait,
503 .parent = &core_l3_ck,
504 .clkdm_name = "core_l4_clkdm",
505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
506 .enable_bit = OMAP24XX_EN_USB_SHIFT,
507 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
508 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
509 .clksel = usb_l4_ick_clksel,
510 .recalc = &omap2_clksel_recalc,
511};
512
513/*
514 * L4 clock management domain
515 *
516 * This domain contains lots of interface clocks from the L4 interface, some
517 * functional clocks. Fixed APLL functional source clocks are managed in
518 * this domain.
519 */
520static const struct clksel_rate l4_core_l3_rates[] = {
521 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
522 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
523 { .div = 0 }
524};
525
526static const struct clksel l4_clksel[] = {
527 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
528 { .parent = NULL }
529};
530
531static struct clk l4_ck = { /* used both as an ick and fck */
532 .name = "l4_ck",
533 .ops = &clkops_null,
534 .parent = &core_l3_ck,
535 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
536 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
537 .clksel = l4_clksel,
538 .recalc = &omap2_clksel_recalc,
539};
540
541/*
542 * SSI is in L3 management domain, its direct parent is core not l3,
543 * many core power domain entities are grouped into the L3 clock
544 * domain.
545 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
546 *
547 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
548 */
549static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
550 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
551 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
552 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
553 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
554 { .div = 5, .val = 5, .flags = RATE_IN_243X },
555 { .div = 0 }
556};
557
558static const struct clksel ssi_ssr_sst_fck_clksel[] = {
559 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
560 { .parent = NULL }
561};
562
563static struct clk ssi_ssr_sst_fck = {
564 .name = "ssi_fck",
565 .ops = &clkops_omap2_dflt_wait,
566 .parent = &core_ck,
567 .clkdm_name = "core_l3_clkdm",
568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
569 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
570 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
571 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
572 .clksel = ssi_ssr_sst_fck_clksel,
573 .recalc = &omap2_clksel_recalc,
574};
575
576/*
577 * Presumably this is the same as SSI_ICLK.
578 * TRM contradicts itself on what clockdomain SSI_ICLK is in
579 */
580static struct clk ssi_l4_ick = {
581 .name = "ssi_l4_ick",
582 .ops = &clkops_omap2_iclk_dflt_wait,
583 .parent = &l4_ck,
584 .clkdm_name = "core_l4_clkdm",
585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
586 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
587 .recalc = &followparent_recalc,
588};
589
590
591/*
592 * GFX clock domain
593 * Clocks:
594 * GFX_FCLK, GFX_ICLK
595 * GFX_CG1(2d), GFX_CG2(3d)
596 *
597 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
598 * The 2d and 3d clocks run at a hardware determined
599 * divided value of fclk.
600 *
601 */
602
603/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
604static const struct clksel gfx_fck_clksel[] = {
605 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
606 { .parent = NULL },
607};
608
609static struct clk gfx_3d_fck = {
610 .name = "gfx_3d_fck",
611 .ops = &clkops_omap2_dflt_wait,
612 .parent = &core_l3_ck,
613 .clkdm_name = "gfx_clkdm",
614 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
615 .enable_bit = OMAP24XX_EN_3D_SHIFT,
616 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
617 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
618 .clksel = gfx_fck_clksel,
619 .recalc = &omap2_clksel_recalc,
620 .round_rate = &omap2_clksel_round_rate,
621 .set_rate = &omap2_clksel_set_rate
622};
623
624static struct clk gfx_2d_fck = {
625 .name = "gfx_2d_fck",
626 .ops = &clkops_omap2_dflt_wait,
627 .parent = &core_l3_ck,
628 .clkdm_name = "gfx_clkdm",
629 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
630 .enable_bit = OMAP24XX_EN_2D_SHIFT,
631 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
632 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
633 .clksel = gfx_fck_clksel,
634 .recalc = &omap2_clksel_recalc,
635};
636
637/* This interface clock does not have a CM_AUTOIDLE bit */
638static struct clk gfx_ick = {
639 .name = "gfx_ick", /* From l3 */
640 .ops = &clkops_omap2_dflt_wait,
641 .parent = &core_l3_ck,
642 .clkdm_name = "gfx_clkdm",
643 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
644 .enable_bit = OMAP_EN_GFX_SHIFT,
645 .recalc = &followparent_recalc,
646};
647
648/*
649 * Modem clock domain (2430)
650 * CLOCKS:
651 * MDM_OSC_CLK
652 * MDM_ICLK
653 * These clocks are usable in chassis mode only.
654 */
655static const struct clksel_rate mdm_ick_core_rates[] = {
656 { .div = 1, .val = 1, .flags = RATE_IN_243X },
657 { .div = 4, .val = 4, .flags = RATE_IN_243X },
658 { .div = 6, .val = 6, .flags = RATE_IN_243X },
659 { .div = 9, .val = 9, .flags = RATE_IN_243X },
660 { .div = 0 }
661};
662
663static const struct clksel mdm_ick_clksel[] = {
664 { .parent = &core_ck, .rates = mdm_ick_core_rates },
665 { .parent = NULL }
666};
667
668static struct clk mdm_ick = { /* used both as a ick and fck */
669 .name = "mdm_ick",
670 .ops = &clkops_omap2_iclk_dflt_wait,
671 .parent = &core_ck,
672 .clkdm_name = "mdm_clkdm",
673 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
674 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
675 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
676 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
677 .clksel = mdm_ick_clksel,
678 .recalc = &omap2_clksel_recalc,
679};
680
681static struct clk mdm_osc_ck = {
682 .name = "mdm_osc_ck",
683 .ops = &clkops_omap2_mdmclk_dflt_wait,
684 .parent = &osc_ck,
685 .clkdm_name = "mdm_clkdm",
686 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
687 .enable_bit = OMAP2430_EN_OSC_SHIFT,
688 .recalc = &followparent_recalc,
689};
690
691/*
692 * DSS clock domain
693 * CLOCKs:
694 * DSS_L4_ICLK, DSS_L3_ICLK,
695 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
696 *
697 * DSS is both initiator and target.
698 */
699/* XXX Add RATE_NOT_VALIDATED */
700
701static const struct clksel_rate dss1_fck_sys_rates[] = {
702 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
703 { .div = 0 }
704};
705
706static const struct clksel_rate dss1_fck_core_rates[] = {
707 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
708 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
709 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
710 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
711 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
712 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
713 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
714 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
715 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
716 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
717 { .div = 0 }
718};
719
720static const struct clksel dss1_fck_clksel[] = {
721 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
722 { .parent = &core_ck, .rates = dss1_fck_core_rates },
723 { .parent = NULL },
724};
725
726static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
727 .name = "dss_ick",
728 .ops = &clkops_omap2_iclk_dflt,
729 .parent = &l4_ck, /* really both l3 and l4 */
730 .clkdm_name = "dss_clkdm",
731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
732 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
733 .recalc = &followparent_recalc,
734};
735
736static struct clk dss1_fck = {
737 .name = "dss1_fck",
738 .ops = &clkops_omap2_dflt,
739 .parent = &core_ck, /* Core or sys */
740 .clkdm_name = "dss_clkdm",
741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
742 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
743 .init = &omap2_init_clksel_parent,
744 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
745 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
746 .clksel = dss1_fck_clksel,
747 .recalc = &omap2_clksel_recalc,
748};
749
750static const struct clksel_rate dss2_fck_sys_rates[] = {
751 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
752 { .div = 0 }
753};
754
755static const struct clksel_rate dss2_fck_48m_rates[] = {
756 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
757 { .div = 0 }
758};
759
760static const struct clksel dss2_fck_clksel[] = {
761 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
762 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
763 { .parent = NULL }
764};
765
766static struct clk dss2_fck = { /* Alt clk used in power management */
767 .name = "dss2_fck",
768 .ops = &clkops_omap2_dflt,
769 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
770 .clkdm_name = "dss_clkdm",
771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
772 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
773 .init = &omap2_init_clksel_parent,
774 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
775 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
776 .clksel = dss2_fck_clksel,
777 .recalc = &omap2_clksel_recalc,
778};
779
780static struct clk dss_54m_fck = { /* Alt clk used in power management */
781 .name = "dss_54m_fck", /* 54m tv clk */
782 .ops = &clkops_omap2_dflt_wait,
783 .parent = &func_54m_ck,
784 .clkdm_name = "dss_clkdm",
785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
786 .enable_bit = OMAP24XX_EN_TV_SHIFT,
787 .recalc = &followparent_recalc,
788};
789
790static struct clk wu_l4_ick = {
791 .name = "wu_l4_ick",
792 .ops = &clkops_null,
793 .parent = &sys_ck,
794 .clkdm_name = "wkup_clkdm",
795 .recalc = &followparent_recalc,
796};
797
798/*
799 * CORE power domain ICLK & FCLK defines.
800 * Many of the these can have more than one possible parent. Entries
801 * here will likely have an L4 interface parent, and may have multiple
802 * functional clock parents.
803 */
804static const struct clksel_rate gpt_alt_rates[] = {
805 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
806 { .div = 0 }
807};
808
809static const struct clksel omap24xx_gpt_clksel[] = {
810 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
811 { .parent = &sys_ck, .rates = gpt_sys_rates },
812 { .parent = &alt_ck, .rates = gpt_alt_rates },
813 { .parent = NULL },
814};
815
816static struct clk gpt1_ick = {
817 .name = "gpt1_ick",
818 .ops = &clkops_omap2_iclk_dflt_wait,
819 .parent = &wu_l4_ick,
820 .clkdm_name = "wkup_clkdm",
821 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
822 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
823 .recalc = &followparent_recalc,
824};
825
826static struct clk gpt1_fck = {
827 .name = "gpt1_fck",
828 .ops = &clkops_omap2_dflt_wait,
829 .parent = &func_32k_ck,
830 .clkdm_name = "core_l4_clkdm",
831 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
832 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
833 .init = &omap2_init_clksel_parent,
834 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
835 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
836 .clksel = omap24xx_gpt_clksel,
837 .recalc = &omap2_clksel_recalc,
838 .round_rate = &omap2_clksel_round_rate,
839 .set_rate = &omap2_clksel_set_rate
840};
841
842static struct clk gpt2_ick = {
843 .name = "gpt2_ick",
844 .ops = &clkops_omap2_iclk_dflt_wait,
845 .parent = &l4_ck,
846 .clkdm_name = "core_l4_clkdm",
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
849 .recalc = &followparent_recalc,
850};
851
852static struct clk gpt2_fck = {
853 .name = "gpt2_fck",
854 .ops = &clkops_omap2_dflt_wait,
855 .parent = &func_32k_ck,
856 .clkdm_name = "core_l4_clkdm",
857 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
859 .init = &omap2_init_clksel_parent,
860 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
861 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
862 .clksel = omap24xx_gpt_clksel,
863 .recalc = &omap2_clksel_recalc,
864};
865
866static struct clk gpt3_ick = {
867 .name = "gpt3_ick",
868 .ops = &clkops_omap2_iclk_dflt_wait,
869 .parent = &l4_ck,
870 .clkdm_name = "core_l4_clkdm",
871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
872 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
873 .recalc = &followparent_recalc,
874};
875
876static struct clk gpt3_fck = {
877 .name = "gpt3_fck",
878 .ops = &clkops_omap2_dflt_wait,
879 .parent = &func_32k_ck,
880 .clkdm_name = "core_l4_clkdm",
881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
882 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
883 .init = &omap2_init_clksel_parent,
884 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
885 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
886 .clksel = omap24xx_gpt_clksel,
887 .recalc = &omap2_clksel_recalc,
888};
889
890static struct clk gpt4_ick = {
891 .name = "gpt4_ick",
892 .ops = &clkops_omap2_iclk_dflt_wait,
893 .parent = &l4_ck,
894 .clkdm_name = "core_l4_clkdm",
895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
896 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
897 .recalc = &followparent_recalc,
898};
899
900static struct clk gpt4_fck = {
901 .name = "gpt4_fck",
902 .ops = &clkops_omap2_dflt_wait,
903 .parent = &func_32k_ck,
904 .clkdm_name = "core_l4_clkdm",
905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
906 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
907 .init = &omap2_init_clksel_parent,
908 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
909 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
910 .clksel = omap24xx_gpt_clksel,
911 .recalc = &omap2_clksel_recalc,
912};
913
914static struct clk gpt5_ick = {
915 .name = "gpt5_ick",
916 .ops = &clkops_omap2_iclk_dflt_wait,
917 .parent = &l4_ck,
918 .clkdm_name = "core_l4_clkdm",
919 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
920 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
921 .recalc = &followparent_recalc,
922};
923
924static struct clk gpt5_fck = {
925 .name = "gpt5_fck",
926 .ops = &clkops_omap2_dflt_wait,
927 .parent = &func_32k_ck,
928 .clkdm_name = "core_l4_clkdm",
929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
930 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
931 .init = &omap2_init_clksel_parent,
932 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
933 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
934 .clksel = omap24xx_gpt_clksel,
935 .recalc = &omap2_clksel_recalc,
936};
937
938static struct clk gpt6_ick = {
939 .name = "gpt6_ick",
940 .ops = &clkops_omap2_iclk_dflt_wait,
941 .parent = &l4_ck,
942 .clkdm_name = "core_l4_clkdm",
943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
944 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
945 .recalc = &followparent_recalc,
946};
947
948static struct clk gpt6_fck = {
949 .name = "gpt6_fck",
950 .ops = &clkops_omap2_dflt_wait,
951 .parent = &func_32k_ck,
952 .clkdm_name = "core_l4_clkdm",
953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
954 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
955 .init = &omap2_init_clksel_parent,
956 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
957 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
958 .clksel = omap24xx_gpt_clksel,
959 .recalc = &omap2_clksel_recalc,
960};
961
962static struct clk gpt7_ick = {
963 .name = "gpt7_ick",
964 .ops = &clkops_omap2_iclk_dflt_wait,
965 .parent = &l4_ck,
966 .clkdm_name = "core_l4_clkdm",
967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
968 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
969 .recalc = &followparent_recalc,
970};
971
972static struct clk gpt7_fck = {
973 .name = "gpt7_fck",
974 .ops = &clkops_omap2_dflt_wait,
975 .parent = &func_32k_ck,
976 .clkdm_name = "core_l4_clkdm",
977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
978 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
979 .init = &omap2_init_clksel_parent,
980 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
981 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
982 .clksel = omap24xx_gpt_clksel,
983 .recalc = &omap2_clksel_recalc,
984};
985
986static struct clk gpt8_ick = {
987 .name = "gpt8_ick",
988 .ops = &clkops_omap2_iclk_dflt_wait,
989 .parent = &l4_ck,
990 .clkdm_name = "core_l4_clkdm",
991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
992 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
993 .recalc = &followparent_recalc,
994};
995
996static struct clk gpt8_fck = {
997 .name = "gpt8_fck",
998 .ops = &clkops_omap2_dflt_wait,
999 .parent = &func_32k_ck,
1000 .clkdm_name = "core_l4_clkdm",
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1003 .init = &omap2_init_clksel_parent,
1004 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1005 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1006 .clksel = omap24xx_gpt_clksel,
1007 .recalc = &omap2_clksel_recalc,
1008};
1009
1010static struct clk gpt9_ick = {
1011 .name = "gpt9_ick",
1012 .ops = &clkops_omap2_iclk_dflt_wait,
1013 .parent = &l4_ck,
1014 .clkdm_name = "core_l4_clkdm",
1015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1016 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1017 .recalc = &followparent_recalc,
1018};
1019
1020static struct clk gpt9_fck = {
1021 .name = "gpt9_fck",
1022 .ops = &clkops_omap2_dflt_wait,
1023 .parent = &func_32k_ck,
1024 .clkdm_name = "core_l4_clkdm",
1025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1026 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1027 .init = &omap2_init_clksel_parent,
1028 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1029 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1030 .clksel = omap24xx_gpt_clksel,
1031 .recalc = &omap2_clksel_recalc,
1032};
1033
1034static struct clk gpt10_ick = {
1035 .name = "gpt10_ick",
1036 .ops = &clkops_omap2_iclk_dflt_wait,
1037 .parent = &l4_ck,
1038 .clkdm_name = "core_l4_clkdm",
1039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1040 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1041 .recalc = &followparent_recalc,
1042};
1043
1044static struct clk gpt10_fck = {
1045 .name = "gpt10_fck",
1046 .ops = &clkops_omap2_dflt_wait,
1047 .parent = &func_32k_ck,
1048 .clkdm_name = "core_l4_clkdm",
1049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1050 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1051 .init = &omap2_init_clksel_parent,
1052 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1053 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1054 .clksel = omap24xx_gpt_clksel,
1055 .recalc = &omap2_clksel_recalc,
1056};
1057
1058static struct clk gpt11_ick = {
1059 .name = "gpt11_ick",
1060 .ops = &clkops_omap2_iclk_dflt_wait,
1061 .parent = &l4_ck,
1062 .clkdm_name = "core_l4_clkdm",
1063 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1064 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1065 .recalc = &followparent_recalc,
1066};
1067
1068static struct clk gpt11_fck = {
1069 .name = "gpt11_fck",
1070 .ops = &clkops_omap2_dflt_wait,
1071 .parent = &func_32k_ck,
1072 .clkdm_name = "core_l4_clkdm",
1073 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1074 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1075 .init = &omap2_init_clksel_parent,
1076 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1077 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1078 .clksel = omap24xx_gpt_clksel,
1079 .recalc = &omap2_clksel_recalc,
1080};
1081
1082static struct clk gpt12_ick = {
1083 .name = "gpt12_ick",
1084 .ops = &clkops_omap2_iclk_dflt_wait,
1085 .parent = &l4_ck,
1086 .clkdm_name = "core_l4_clkdm",
1087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1088 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1089 .recalc = &followparent_recalc,
1090};
1091
1092static struct clk gpt12_fck = {
1093 .name = "gpt12_fck",
1094 .ops = &clkops_omap2_dflt_wait,
1095 .parent = &secure_32k_ck,
1096 .clkdm_name = "core_l4_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1098 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1099 .init = &omap2_init_clksel_parent,
1100 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1101 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1102 .clksel = omap24xx_gpt_clksel,
1103 .recalc = &omap2_clksel_recalc,
1104};
1105
1106static struct clk mcbsp1_ick = {
1107 .name = "mcbsp1_ick",
1108 .ops = &clkops_omap2_iclk_dflt_wait,
1109 .parent = &l4_ck,
1110 .clkdm_name = "core_l4_clkdm",
1111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1112 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1113 .recalc = &followparent_recalc,
1114};
1115
1116static const struct clksel_rate common_mcbsp_96m_rates[] = {
1117 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1118 { .div = 0 }
1119};
1120
1121static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1122 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1123 { .div = 0 }
1124};
1125
1126static const struct clksel mcbsp_fck_clksel[] = {
1127 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1128 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1129 { .parent = NULL }
1130};
1131
1132static struct clk mcbsp1_fck = {
1133 .name = "mcbsp1_fck",
1134 .ops = &clkops_omap2_dflt_wait,
1135 .parent = &func_96m_ck,
1136 .init = &omap2_init_clksel_parent,
1137 .clkdm_name = "core_l4_clkdm",
1138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1139 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1140 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1141 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1142 .clksel = mcbsp_fck_clksel,
1143 .recalc = &omap2_clksel_recalc,
1144};
1145
1146static struct clk mcbsp2_ick = {
1147 .name = "mcbsp2_ick",
1148 .ops = &clkops_omap2_iclk_dflt_wait,
1149 .parent = &l4_ck,
1150 .clkdm_name = "core_l4_clkdm",
1151 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1152 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1153 .recalc = &followparent_recalc,
1154};
1155
1156static struct clk mcbsp2_fck = {
1157 .name = "mcbsp2_fck",
1158 .ops = &clkops_omap2_dflt_wait,
1159 .parent = &func_96m_ck,
1160 .init = &omap2_init_clksel_parent,
1161 .clkdm_name = "core_l4_clkdm",
1162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1163 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1164 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1165 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1166 .clksel = mcbsp_fck_clksel,
1167 .recalc = &omap2_clksel_recalc,
1168};
1169
1170static struct clk mcbsp3_ick = {
1171 .name = "mcbsp3_ick",
1172 .ops = &clkops_omap2_iclk_dflt_wait,
1173 .parent = &l4_ck,
1174 .clkdm_name = "core_l4_clkdm",
1175 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1176 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1177 .recalc = &followparent_recalc,
1178};
1179
1180static struct clk mcbsp3_fck = {
1181 .name = "mcbsp3_fck",
1182 .ops = &clkops_omap2_dflt_wait,
1183 .parent = &func_96m_ck,
1184 .init = &omap2_init_clksel_parent,
1185 .clkdm_name = "core_l4_clkdm",
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1187 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1188 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1189 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1190 .clksel = mcbsp_fck_clksel,
1191 .recalc = &omap2_clksel_recalc,
1192};
1193
1194static struct clk mcbsp4_ick = {
1195 .name = "mcbsp4_ick",
1196 .ops = &clkops_omap2_iclk_dflt_wait,
1197 .parent = &l4_ck,
1198 .clkdm_name = "core_l4_clkdm",
1199 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1200 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1201 .recalc = &followparent_recalc,
1202};
1203
1204static struct clk mcbsp4_fck = {
1205 .name = "mcbsp4_fck",
1206 .ops = &clkops_omap2_dflt_wait,
1207 .parent = &func_96m_ck,
1208 .init = &omap2_init_clksel_parent,
1209 .clkdm_name = "core_l4_clkdm",
1210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1211 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1212 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1213 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1214 .clksel = mcbsp_fck_clksel,
1215 .recalc = &omap2_clksel_recalc,
1216};
1217
1218static struct clk mcbsp5_ick = {
1219 .name = "mcbsp5_ick",
1220 .ops = &clkops_omap2_iclk_dflt_wait,
1221 .parent = &l4_ck,
1222 .clkdm_name = "core_l4_clkdm",
1223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1224 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1225 .recalc = &followparent_recalc,
1226};
1227
1228static struct clk mcbsp5_fck = {
1229 .name = "mcbsp5_fck",
1230 .ops = &clkops_omap2_dflt_wait,
1231 .parent = &func_96m_ck,
1232 .init = &omap2_init_clksel_parent,
1233 .clkdm_name = "core_l4_clkdm",
1234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1235 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1236 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1237 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1238 .clksel = mcbsp_fck_clksel,
1239 .recalc = &omap2_clksel_recalc,
1240};
1241
1242static struct clk mcspi1_ick = {
1243 .name = "mcspi1_ick",
1244 .ops = &clkops_omap2_iclk_dflt_wait,
1245 .parent = &l4_ck,
1246 .clkdm_name = "core_l4_clkdm",
1247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1248 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1249 .recalc = &followparent_recalc,
1250};
1251
1252static struct clk mcspi1_fck = {
1253 .name = "mcspi1_fck",
1254 .ops = &clkops_omap2_dflt_wait,
1255 .parent = &func_48m_ck,
1256 .clkdm_name = "core_l4_clkdm",
1257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1258 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1259 .recalc = &followparent_recalc,
1260};
1261
1262static struct clk mcspi2_ick = {
1263 .name = "mcspi2_ick",
1264 .ops = &clkops_omap2_iclk_dflt_wait,
1265 .parent = &l4_ck,
1266 .clkdm_name = "core_l4_clkdm",
1267 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1268 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1269 .recalc = &followparent_recalc,
1270};
1271
1272static struct clk mcspi2_fck = {
1273 .name = "mcspi2_fck",
1274 .ops = &clkops_omap2_dflt_wait,
1275 .parent = &func_48m_ck,
1276 .clkdm_name = "core_l4_clkdm",
1277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1278 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1279 .recalc = &followparent_recalc,
1280};
1281
1282static struct clk mcspi3_ick = {
1283 .name = "mcspi3_ick",
1284 .ops = &clkops_omap2_iclk_dflt_wait,
1285 .parent = &l4_ck,
1286 .clkdm_name = "core_l4_clkdm",
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1288 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1289 .recalc = &followparent_recalc,
1290};
1291
1292static struct clk mcspi3_fck = {
1293 .name = "mcspi3_fck",
1294 .ops = &clkops_omap2_dflt_wait,
1295 .parent = &func_48m_ck,
1296 .clkdm_name = "core_l4_clkdm",
1297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1298 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1299 .recalc = &followparent_recalc,
1300};
1301
1302static struct clk uart1_ick = {
1303 .name = "uart1_ick",
1304 .ops = &clkops_omap2_iclk_dflt_wait,
1305 .parent = &l4_ck,
1306 .clkdm_name = "core_l4_clkdm",
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1308 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1309 .recalc = &followparent_recalc,
1310};
1311
1312static struct clk uart1_fck = {
1313 .name = "uart1_fck",
1314 .ops = &clkops_omap2_dflt_wait,
1315 .parent = &func_48m_ck,
1316 .clkdm_name = "core_l4_clkdm",
1317 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1318 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1319 .recalc = &followparent_recalc,
1320};
1321
1322static struct clk uart2_ick = {
1323 .name = "uart2_ick",
1324 .ops = &clkops_omap2_iclk_dflt_wait,
1325 .parent = &l4_ck,
1326 .clkdm_name = "core_l4_clkdm",
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1328 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1329 .recalc = &followparent_recalc,
1330};
1331
1332static struct clk uart2_fck = {
1333 .name = "uart2_fck",
1334 .ops = &clkops_omap2_dflt_wait,
1335 .parent = &func_48m_ck,
1336 .clkdm_name = "core_l4_clkdm",
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1338 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1339 .recalc = &followparent_recalc,
1340};
1341
1342static struct clk uart3_ick = {
1343 .name = "uart3_ick",
1344 .ops = &clkops_omap2_iclk_dflt_wait,
1345 .parent = &l4_ck,
1346 .clkdm_name = "core_l4_clkdm",
1347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1348 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1349 .recalc = &followparent_recalc,
1350};
1351
1352static struct clk uart3_fck = {
1353 .name = "uart3_fck",
1354 .ops = &clkops_omap2_dflt_wait,
1355 .parent = &func_48m_ck,
1356 .clkdm_name = "core_l4_clkdm",
1357 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1358 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1359 .recalc = &followparent_recalc,
1360};
1361
1362static struct clk gpios_ick = {
1363 .name = "gpios_ick",
1364 .ops = &clkops_omap2_iclk_dflt_wait,
1365 .parent = &wu_l4_ick,
1366 .clkdm_name = "wkup_clkdm",
1367 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1368 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1369 .recalc = &followparent_recalc,
1370};
1371
1372static struct clk gpios_fck = {
1373 .name = "gpios_fck",
1374 .ops = &clkops_omap2_dflt_wait,
1375 .parent = &func_32k_ck,
1376 .clkdm_name = "wkup_clkdm",
1377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1378 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1379 .recalc = &followparent_recalc,
1380};
1381
1382static struct clk mpu_wdt_ick = {
1383 .name = "mpu_wdt_ick",
1384 .ops = &clkops_omap2_iclk_dflt_wait,
1385 .parent = &wu_l4_ick,
1386 .clkdm_name = "wkup_clkdm",
1387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1388 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1389 .recalc = &followparent_recalc,
1390};
1391
1392static struct clk mpu_wdt_fck = {
1393 .name = "mpu_wdt_fck",
1394 .ops = &clkops_omap2_dflt_wait,
1395 .parent = &func_32k_ck,
1396 .clkdm_name = "wkup_clkdm",
1397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1398 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1399 .recalc = &followparent_recalc,
1400};
1401
1402static struct clk sync_32k_ick = {
1403 .name = "sync_32k_ick",
1404 .ops = &clkops_omap2_iclk_dflt_wait,
1405 .flags = ENABLE_ON_INIT,
1406 .parent = &wu_l4_ick,
1407 .clkdm_name = "wkup_clkdm",
1408 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1409 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1410 .recalc = &followparent_recalc,
1411};
1412
1413static struct clk wdt1_ick = {
1414 .name = "wdt1_ick",
1415 .ops = &clkops_omap2_iclk_dflt_wait,
1416 .parent = &wu_l4_ick,
1417 .clkdm_name = "wkup_clkdm",
1418 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1419 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1420 .recalc = &followparent_recalc,
1421};
1422
1423static struct clk omapctrl_ick = {
1424 .name = "omapctrl_ick",
1425 .ops = &clkops_omap2_iclk_dflt_wait,
1426 .flags = ENABLE_ON_INIT,
1427 .parent = &wu_l4_ick,
1428 .clkdm_name = "wkup_clkdm",
1429 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1430 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1431 .recalc = &followparent_recalc,
1432};
1433
1434static struct clk icr_ick = {
1435 .name = "icr_ick",
1436 .ops = &clkops_omap2_iclk_dflt_wait,
1437 .parent = &wu_l4_ick,
1438 .clkdm_name = "wkup_clkdm",
1439 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1440 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1441 .recalc = &followparent_recalc,
1442};
1443
1444static struct clk cam_ick = {
1445 .name = "cam_ick",
1446 .ops = &clkops_omap2_iclk_dflt,
1447 .parent = &l4_ck,
1448 .clkdm_name = "core_l4_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1450 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1451 .recalc = &followparent_recalc,
1452};
1453
1454/*
1455 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1456 * split into two separate clocks, since the parent clocks are different
1457 * and the clockdomains are also different.
1458 */
1459static struct clk cam_fck = {
1460 .name = "cam_fck",
1461 .ops = &clkops_omap2_dflt,
1462 .parent = &func_96m_ck,
1463 .clkdm_name = "core_l3_clkdm",
1464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1466 .recalc = &followparent_recalc,
1467};
1468
1469static struct clk mailboxes_ick = {
1470 .name = "mailboxes_ick",
1471 .ops = &clkops_omap2_iclk_dflt_wait,
1472 .parent = &l4_ck,
1473 .clkdm_name = "core_l4_clkdm",
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1475 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk wdt4_ick = {
1480 .name = "wdt4_ick",
1481 .ops = &clkops_omap2_iclk_dflt_wait,
1482 .parent = &l4_ck,
1483 .clkdm_name = "core_l4_clkdm",
1484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1485 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1486 .recalc = &followparent_recalc,
1487};
1488
1489static struct clk wdt4_fck = {
1490 .name = "wdt4_fck",
1491 .ops = &clkops_omap2_dflt_wait,
1492 .parent = &func_32k_ck,
1493 .clkdm_name = "core_l4_clkdm",
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1496 .recalc = &followparent_recalc,
1497};
1498
1499static struct clk mspro_ick = {
1500 .name = "mspro_ick",
1501 .ops = &clkops_omap2_iclk_dflt_wait,
1502 .parent = &l4_ck,
1503 .clkdm_name = "core_l4_clkdm",
1504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1505 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1506 .recalc = &followparent_recalc,
1507};
1508
1509static struct clk mspro_fck = {
1510 .name = "mspro_fck",
1511 .ops = &clkops_omap2_dflt_wait,
1512 .parent = &func_96m_ck,
1513 .clkdm_name = "core_l4_clkdm",
1514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1516 .recalc = &followparent_recalc,
1517};
1518
1519static struct clk fac_ick = {
1520 .name = "fac_ick",
1521 .ops = &clkops_omap2_iclk_dflt_wait,
1522 .parent = &l4_ck,
1523 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1525 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1526 .recalc = &followparent_recalc,
1527};
1528
1529static struct clk fac_fck = {
1530 .name = "fac_fck",
1531 .ops = &clkops_omap2_dflt_wait,
1532 .parent = &func_12m_ck,
1533 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1535 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1536 .recalc = &followparent_recalc,
1537};
1538
1539static struct clk hdq_ick = {
1540 .name = "hdq_ick",
1541 .ops = &clkops_omap2_iclk_dflt_wait,
1542 .parent = &l4_ck,
1543 .clkdm_name = "core_l4_clkdm",
1544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1545 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1546 .recalc = &followparent_recalc,
1547};
1548
1549static struct clk hdq_fck = {
1550 .name = "hdq_fck",
1551 .ops = &clkops_omap2_dflt_wait,
1552 .parent = &func_12m_ck,
1553 .clkdm_name = "core_l4_clkdm",
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1555 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1556 .recalc = &followparent_recalc,
1557};
1558
1559/*
1560 * XXX This is marked as a 2420-only define, but it claims to be present
1561 * on 2430 also. Double-check.
1562 */
1563static struct clk i2c2_ick = {
1564 .name = "i2c2_ick",
1565 .ops = &clkops_omap2_iclk_dflt_wait,
1566 .parent = &l4_ck,
1567 .clkdm_name = "core_l4_clkdm",
1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1569 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1570 .recalc = &followparent_recalc,
1571};
1572
1573static struct clk i2chs2_fck = {
1574 .name = "i2chs2_fck",
1575 .ops = &clkops_omap2430_i2chs_wait,
1576 .parent = &func_96m_ck,
1577 .clkdm_name = "core_l4_clkdm",
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1579 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1580 .recalc = &followparent_recalc,
1581};
1582
1583/*
1584 * XXX This is marked as a 2420-only define, but it claims to be present
1585 * on 2430 also. Double-check.
1586 */
1587static struct clk i2c1_ick = {
1588 .name = "i2c1_ick",
1589 .ops = &clkops_omap2_iclk_dflt_wait,
1590 .parent = &l4_ck,
1591 .clkdm_name = "core_l4_clkdm",
1592 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1593 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1594 .recalc = &followparent_recalc,
1595};
1596
1597static struct clk i2chs1_fck = {
1598 .name = "i2chs1_fck",
1599 .ops = &clkops_omap2430_i2chs_wait,
1600 .parent = &func_96m_ck,
1601 .clkdm_name = "core_l4_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1603 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1604 .recalc = &followparent_recalc,
1605};
1606
1607/*
1608 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1609 * accesses derived from this data.
1610 */
1611static struct clk gpmc_fck = {
1612 .name = "gpmc_fck",
1613 .ops = &clkops_omap2_iclk_idle_only,
1614 .parent = &core_l3_ck,
1615 .flags = ENABLE_ON_INIT,
1616 .clkdm_name = "core_l3_clkdm",
1617 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1618 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1619 .recalc = &followparent_recalc,
1620};
1621
1622static struct clk sdma_fck = {
1623 .name = "sdma_fck",
1624 .ops = &clkops_null, /* RMK: missing? */
1625 .parent = &core_l3_ck,
1626 .clkdm_name = "core_l3_clkdm",
1627 .recalc = &followparent_recalc,
1628};
1629
1630/*
1631 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1632 * accesses derived from this data.
1633 */
1634static struct clk sdma_ick = {
1635 .name = "sdma_ick",
1636 .ops = &clkops_omap2_iclk_idle_only,
1637 .parent = &core_l3_ck,
1638 .clkdm_name = "core_l3_clkdm",
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1640 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1641 .recalc = &followparent_recalc,
1642};
1643
1644static struct clk sdrc_ick = {
1645 .name = "sdrc_ick",
1646 .ops = &clkops_omap2_iclk_idle_only,
1647 .parent = &core_l3_ck,
1648 .flags = ENABLE_ON_INIT,
1649 .clkdm_name = "core_l3_clkdm",
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1651 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1652 .recalc = &followparent_recalc,
1653};
1654
1655static struct clk des_ick = {
1656 .name = "des_ick",
1657 .ops = &clkops_omap2_iclk_dflt_wait,
1658 .parent = &l4_ck,
1659 .clkdm_name = "core_l4_clkdm",
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1661 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1662 .recalc = &followparent_recalc,
1663};
1664
1665static struct clk sha_ick = {
1666 .name = "sha_ick",
1667 .ops = &clkops_omap2_iclk_dflt_wait,
1668 .parent = &l4_ck,
1669 .clkdm_name = "core_l4_clkdm",
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1671 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1672 .recalc = &followparent_recalc,
1673};
1674
1675static struct clk rng_ick = {
1676 .name = "rng_ick",
1677 .ops = &clkops_omap2_iclk_dflt_wait,
1678 .parent = &l4_ck,
1679 .clkdm_name = "core_l4_clkdm",
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1681 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1682 .recalc = &followparent_recalc,
1683};
1684
1685static struct clk aes_ick = {
1686 .name = "aes_ick",
1687 .ops = &clkops_omap2_iclk_dflt_wait,
1688 .parent = &l4_ck,
1689 .clkdm_name = "core_l4_clkdm",
1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1691 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1692 .recalc = &followparent_recalc,
1693};
1694
1695static struct clk pka_ick = {
1696 .name = "pka_ick",
1697 .ops = &clkops_omap2_iclk_dflt_wait,
1698 .parent = &l4_ck,
1699 .clkdm_name = "core_l4_clkdm",
1700 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1701 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1702 .recalc = &followparent_recalc,
1703};
1704
1705static struct clk usb_fck = {
1706 .name = "usb_fck",
1707 .ops = &clkops_omap2_dflt_wait,
1708 .parent = &func_48m_ck,
1709 .clkdm_name = "core_l3_clkdm",
1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1711 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1712 .recalc = &followparent_recalc,
1713};
1714
1715static struct clk usbhs_ick = {
1716 .name = "usbhs_ick",
1717 .ops = &clkops_omap2_iclk_dflt_wait,
1718 .parent = &core_l3_ck,
1719 .clkdm_name = "core_l3_clkdm",
1720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1721 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1722 .recalc = &followparent_recalc,
1723};
1724
1725static struct clk mmchs1_ick = {
1726 .name = "mmchs1_ick",
1727 .ops = &clkops_omap2_iclk_dflt_wait,
1728 .parent = &l4_ck,
1729 .clkdm_name = "core_l4_clkdm",
1730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1731 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1732 .recalc = &followparent_recalc,
1733};
1734
1735static struct clk mmchs1_fck = {
1736 .name = "mmchs1_fck",
1737 .ops = &clkops_omap2_dflt_wait,
1738 .parent = &func_96m_ck,
1739 .clkdm_name = "core_l4_clkdm",
1740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1741 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1742 .recalc = &followparent_recalc,
1743};
1744
1745static struct clk mmchs2_ick = {
1746 .name = "mmchs2_ick",
1747 .ops = &clkops_omap2_iclk_dflt_wait,
1748 .parent = &l4_ck,
1749 .clkdm_name = "core_l4_clkdm",
1750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1751 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1752 .recalc = &followparent_recalc,
1753};
1754
1755static struct clk mmchs2_fck = {
1756 .name = "mmchs2_fck",
1757 .ops = &clkops_omap2_dflt_wait,
1758 .parent = &func_96m_ck,
1759 .clkdm_name = "core_l4_clkdm",
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1761 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1762 .recalc = &followparent_recalc,
1763};
1764
1765static struct clk gpio5_ick = {
1766 .name = "gpio5_ick",
1767 .ops = &clkops_omap2_iclk_dflt_wait,
1768 .parent = &l4_ck,
1769 .clkdm_name = "core_l4_clkdm",
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1771 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1772 .recalc = &followparent_recalc,
1773};
1774
1775static struct clk gpio5_fck = {
1776 .name = "gpio5_fck",
1777 .ops = &clkops_omap2_dflt_wait,
1778 .parent = &func_32k_ck,
1779 .clkdm_name = "core_l4_clkdm",
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1781 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1782 .recalc = &followparent_recalc,
1783};
1784
1785static struct clk mdm_intc_ick = {
1786 .name = "mdm_intc_ick",
1787 .ops = &clkops_omap2_iclk_dflt_wait,
1788 .parent = &l4_ck,
1789 .clkdm_name = "core_l4_clkdm",
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1791 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1792 .recalc = &followparent_recalc,
1793};
1794
1795static struct clk mmchsdb1_fck = {
1796 .name = "mmchsdb1_fck",
1797 .ops = &clkops_omap2_dflt_wait,
1798 .parent = &func_32k_ck,
1799 .clkdm_name = "core_l4_clkdm",
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1801 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1802 .recalc = &followparent_recalc,
1803};
1804
1805static struct clk mmchsdb2_fck = {
1806 .name = "mmchsdb2_fck",
1807 .ops = &clkops_omap2_dflt_wait,
1808 .parent = &func_32k_ck,
1809 .clkdm_name = "core_l4_clkdm",
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1811 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1812 .recalc = &followparent_recalc,
1813};
1814
1815/*
1816 * This clock is a composite clock which does entire set changes then
1817 * forces a rebalance. It keys on the MPU speed, but it really could
1818 * be any key speed part of a set in the rate table.
1819 *
1820 * to really change a set, you need memory table sets which get changed
1821 * in sram, pre-notifiers & post notifiers, changing the top set, without
1822 * having low level display recalc's won't work... this is why dpm notifiers
1823 * work, isr's off, walk a list of clocks already _off_ and not messing with
1824 * the bus.
1825 *
1826 * This clock should have no parent. It embodies the entire upper level
1827 * active set. A parent will mess up some of the init also.
1828 */
1829static struct clk virt_prcm_set = {
1830 .name = "virt_prcm_set",
1831 .ops = &clkops_null,
1832 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1833 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1834 .set_rate = &omap2_select_table_rate,
1835 .round_rate = &omap2_round_to_table_rate,
1836};
1837
1838
1839/*
1840 * clkdev integration
1841 */
1842
1843static struct omap_clk omap2430_clks[] = {
1844 /* external root sources */
1845 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1846 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1847 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1848 CLK("twl", "fck", &osc_ck, CK_243X),
1849 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1850 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1851 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1852 /* internal analog sources */
1853 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1854 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1855 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1856 /* internal prcm root sources */
1857 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1858 CLK(NULL, "core_ck", &core_ck, CK_243X),
1859 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1860 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1861 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1862 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1863 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1864 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1865 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1866 /* mpu domain clocks */
1867 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1868 /* dsp domain clocks */
1869 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1870 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1871 /* GFX domain clocks */
1872 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1873 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1874 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1875 /* Modem domain clocks */
1876 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1877 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1878 /* DSS domain clocks */
1879 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1880 CLK(NULL, "dss_ick", &dss_ick, CK_243X),
1881 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1882 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1883 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1884 /* L3 domain clocks */
1885 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1886 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1887 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1888 /* L4 domain clocks */
1889 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1890 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1891 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1892 /* virtual meta-group clock */
1893 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1894 /* general l4 interface ck, multi-parent functional clk */
1895 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1896 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1897 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1898 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1899 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1900 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1901 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1902 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1903 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1904 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1905 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1906 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1907 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1908 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1909 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1910 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1911 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1912 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1913 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1914 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1915 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1916 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1917 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1918 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1919 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1920 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
1921 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1922 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1923 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
1924 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1925 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1926 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
1927 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1928 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1929 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
1930 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1931 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1932 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
1933 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1934 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1935 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
1936 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1937 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1938 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
1939 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1940 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1941 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
1942 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1943 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1944 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1945 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1946 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1947 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1948 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1949 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1950 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1951 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1952 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
1953 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1954 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1955 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1956 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1957 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1958 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1959 CLK(NULL, "cam_fck", &cam_fck, CK_243X),
1960 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1961 CLK(NULL, "cam_ick", &cam_ick, CK_243X),
1962 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1963 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1964 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1965 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1966 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1967 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1968 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1969 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1970 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
1971 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1972 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
1973 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1974 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
1975 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1976 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1977 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
1978 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1979 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1980 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1981 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1982 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1983 CLK(NULL, "des_ick", &des_ick, CK_243X),
1984 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1985 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1986 CLK(NULL, "rng_ick", &rng_ick, CK_243X),
1987 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1988 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1989 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1990 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1991 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1993 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
1994 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1995 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1996 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
1997 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1998 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1999 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2000 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2001 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2002 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
2003 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2004 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
2005 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2006 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2007 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2008 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
2009};
2010
2011/*
2012 * init code
2013 */
2014
2015int __init omap2430_clk_init(void)
2016{
2017 struct omap_clk *c;
2018
2019 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2020 cpu_mask = RATE_IN_243X;
2021 rate_table = omap2430_rate_table;
2022
2023 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2024 c++)
2025 clk_preinit(c->lk.clk);
2026
2027 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2028 propagate_rate(&osc_ck);
2029 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2030 propagate_rate(&sys_ck);
2031
2032 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2033 c++) {
2034 clkdev_add(&c->lk);
2035 clk_register(c->lk.clk);
2036 omap2_init_clk_clkdm(c->lk.clk);
2037 }
2038
2039 omap2xxx_clkt_vps_late_init();
2040
2041 /* Disable autoidle on all clocks; let the PM code enable it later */
2042 omap_clk_disable_autoidle_all();
2043
2044 /* XXX Can this be done from the virt_prcm_set clk init function? */
2045 omap2xxx_clkt_vps_check_bootloader_rates();
2046
2047 recalculate_root_clocks();
2048
2049 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2050 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2051 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2052
2053 /*
2054 * Only enable those clocks we will need, let the drivers
2055 * enable other clocks as necessary
2056 */
2057 clk_enable_init_clocks();
2058
2059 return 0;
2060}
2061
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