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authorTony Lindgren <tony@atomide.com>2012-04-19 20:45:33 -0400
committerTony Lindgren <tony@atomide.com>2012-04-19 20:45:33 -0400
commit1df82cd6d7673006ae2ecbe8745bcf44f61c53a8 (patch)
tree737dbba397924c3b566878012ab6fef7fa7dfafe /arch/arm/mach-omap2
parent9c3a3009f1c66f4a758b1e5d31b6977185d70a56 (diff)
parent96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 (diff)
Merge tag 'omap-devel-a-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-hwmod
Add in most of the remaining hwmods (IP block descriptions) for the OMAP44xx family of SoCs. There still seem to be a few missing, such as those for the MMU IP blocks, but this seems to cover the bulk of the remainder.
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile8
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c6
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c10
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains_common_data.c24
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c1416
6 files changed, 1418 insertions, 48 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 49f92bc1c311..d8604a3e490e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -118,16 +118,18 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
118 powerdomains44xx_data.o 118 powerdomains44xx_data.o
119 119
120# PRCM clockdomain control 120# PRCM clockdomain control
121obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ 121clockdomain-common += clockdomain.o \
122 clockdomains_common_data.o
123obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) \
122 clockdomain2xxx_3xxx.o \ 124 clockdomain2xxx_3xxx.o \
123 clockdomains2xxx_3xxx_data.o 125 clockdomains2xxx_3xxx_data.o
124obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o 126obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
125obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o 127obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
126obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ 128obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) \
127 clockdomain2xxx_3xxx.o \ 129 clockdomain2xxx_3xxx.o \
128 clockdomains2xxx_3xxx_data.o \ 130 clockdomains2xxx_3xxx_data.o \
129 clockdomains3xxx_data.o 131 clockdomains3xxx_data.o
130obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ 132obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) \
131 clockdomain44xx.o \ 133 clockdomain44xx.o \
132 clockdomains44xx_data.o 134 clockdomains44xx_data.o
133 135
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 935c7f03dab9..4f04dd11d655 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
51 struct clkdm_dep *cd; 51 struct clkdm_dep *cd;
52 u32 mask = 0; 52 u32 mask = 0;
53 53
54 if (!clkdm->prcm_partition)
55 return 0;
56
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 57 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!cd->clkdm) 58 if (!cd->clkdm)
56 continue; /* only happens if data is erroneous */ 59 continue; /* only happens if data is erroneous */
@@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
103{ 106{
104 bool hwsup = false; 107 bool hwsup = false;
105 108
109 if (!clkdm->prcm_partition)
110 return 0;
111
106 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 112 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
107 clkdm->cm_inst, clkdm->clkdm_offs); 113 clkdm->cm_inst, clkdm->clkdm_offs);
108 114
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 0a6a04897d89..839145e1cfbe 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
89 .pwrdm = { .name = "wkup_pwrdm" }, 89 .pwrdm = { .name = "wkup_pwrdm" },
90 .dep_bit = OMAP_EN_WKUP_SHIFT, 90 .dep_bit = OMAP_EN_WKUP_SHIFT,
91}; 91};
92
93struct clockdomain prm_common_clkdm = {
94 .name = "prm_clkdm",
95 .pwrdm = { .name = "wkup_pwrdm" },
96};
97
98struct clockdomain cm_common_clkdm = {
99 .name = "cm_clkdm",
100 .pwrdm = { .name = "core_pwrdm" },
101};
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index bd7ed13515cc..c53425847493 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
430 &l4_wkup_44xx_clkdm, 430 &l4_wkup_44xx_clkdm,
431 &emu_sys_44xx_clkdm, 431 &emu_sys_44xx_clkdm,
432 &l3_dma_44xx_clkdm, 432 &l3_dma_44xx_clkdm,
433 &prm_common_clkdm,
434 &cm_common_clkdm,
433 NULL 435 NULL
434}; 436};
435 437
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
new file mode 100644
index 000000000000..615b1f04967d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_common_data.c
@@ -0,0 +1,24 @@
1/*
2 * OMAP2+-common clockdomain data
3 *
4 * Copyright (C) 2008-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 */
9
10#include <linux/kernel.h>
11#include <linux/io.h>
12
13#include "clockdomain.h"
14
15/* These are implicit clockdomains - they are never defined as such in TRM */
16struct clockdomain prm_common_clkdm = {
17 .name = "prm_clkdm",
18 .pwrdm = { .name = "wkup_pwrdm" },
19};
20
21struct clockdomain cm_common_clkdm = {
22 .name = "cm_clkdm",
23 .pwrdm = { .name = "core_pwrdm" },
24};
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d91dec5b4bc..49061295475c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -51,6 +51,27 @@
51 */ 51 */
52 52
53/* 53/*
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
56 */
57static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
58 .name = "c2c_target_fw",
59};
60
61/* c2c_target_fw */
62static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
63 .name = "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class,
65 .clkdm_name = "d2d_clkdm",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
69 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
70 },
71 },
72};
73
74/*
54 * 'dmm' class 75 * 'dmm' class
55 * instance(s): dmm 76 * instance(s): dmm
56 */ 77 */
@@ -242,6 +263,28 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
242}; 263};
243 264
244/* 265/*
266 * 'ocp_wp_noc' class
267 * instance(s): ocp_wp_noc
268 */
269static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
270 .name = "ocp_wp_noc",
271};
272
273/* ocp_wp_noc */
274static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
275 .name = "ocp_wp_noc",
276 .class = &omap44xx_ocp_wp_noc_hwmod_class,
277 .clkdm_name = "l3_instr_clkdm",
278 .prcm = {
279 .omap4 = {
280 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
281 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
282 .modulemode = MODULEMODE_HWCTRL,
283 },
284 },
285};
286
287/*
245 * Modules omap_hwmod structures 288 * Modules omap_hwmod structures
246 * 289 *
247 * The following IPs are excluded for the moment because: 290 * The following IPs are excluded for the moment because:
@@ -249,41 +292,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
249 * - They still need to be validated with the driver 292 * - They still need to be validated with the driver
250 * properly adapted to omap_hwmod / omap_device 293 * properly adapted to omap_hwmod / omap_device
251 * 294 *
252 * c2c 295 * usim
253 * c2c_target_fw
254 * cm_core
255 * cm_core_aon
256 * ctrl_module_core
257 * ctrl_module_pad_core
258 * ctrl_module_pad_wkup
259 * ctrl_module_wkup
260 * debugss
261 * efuse_ctrl_cust
262 * efuse_ctrl_std
263 * elm
264 * emif1
265 * emif2
266 * fdif
267 * gpmc
268 * gpu
269 * hdq1w
270 * mcasp
271 * mpu_c0
272 * mpu_c1
273 * ocmc_ram
274 * ocp2scp_usb_phy
275 * ocp_wp_noc
276 * prcm_mpu
277 * prm
278 * scrm
279 * sl2if
280 * slimbus1
281 * slimbus2
282 * usb_host_fs
283 * usb_host_hs
284 * usb_phy_cm
285 * usb_tll_hs
286 * usim
287 */ 296 */
288 297
289/* 298/*
@@ -341,6 +350,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
341}; 350};
342 351
343/* 352/*
353 * 'c2c' class
354 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
355 * soc
356 */
357
358static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
359 .name = "c2c",
360};
361
362/* c2c */
363static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
364 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
365 { .irq = -1 }
366};
367
368static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
369 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
370 { .dma_req = -1 }
371};
372
373static struct omap_hwmod omap44xx_c2c_hwmod = {
374 .name = "c2c",
375 .class = &omap44xx_c2c_hwmod_class,
376 .clkdm_name = "d2d_clkdm",
377 .mpu_irqs = omap44xx_c2c_irqs,
378 .sdma_reqs = omap44xx_c2c_sdma_reqs,
379 .prcm = {
380 .omap4 = {
381 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
382 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
383 },
384 },
385};
386
387/*
344 * 'counter' class 388 * 'counter' class
345 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 389 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
346 */ 390 */
@@ -375,6 +419,83 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
375}; 419};
376 420
377/* 421/*
422 * 'ctrl_module' class
423 * attila core control module + core pad control module + wkup pad control
424 * module + attila wkup control module
425 */
426
427static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
428 .rev_offs = 0x0000,
429 .sysc_offs = 0x0010,
430 .sysc_flags = SYSC_HAS_SIDLEMODE,
431 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
432 SIDLE_SMART_WKUP),
433 .sysc_fields = &omap_hwmod_sysc_type2,
434};
435
436static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
437 .name = "ctrl_module",
438 .sysc = &omap44xx_ctrl_module_sysc,
439};
440
441/* ctrl_module_core */
442static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
443 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
444 { .irq = -1 }
445};
446
447static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
448 .name = "ctrl_module_core",
449 .class = &omap44xx_ctrl_module_hwmod_class,
450 .clkdm_name = "l4_cfg_clkdm",
451 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
452};
453
454/* ctrl_module_pad_core */
455static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
456 .name = "ctrl_module_pad_core",
457 .class = &omap44xx_ctrl_module_hwmod_class,
458 .clkdm_name = "l4_cfg_clkdm",
459};
460
461/* ctrl_module_wkup */
462static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
463 .name = "ctrl_module_wkup",
464 .class = &omap44xx_ctrl_module_hwmod_class,
465 .clkdm_name = "l4_wkup_clkdm",
466};
467
468/* ctrl_module_pad_wkup */
469static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
470 .name = "ctrl_module_pad_wkup",
471 .class = &omap44xx_ctrl_module_hwmod_class,
472 .clkdm_name = "l4_wkup_clkdm",
473};
474
475/*
476 * 'debugss' class
477 * debug and emulation sub system
478 */
479
480static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
481 .name = "debugss",
482};
483
484/* debugss */
485static struct omap_hwmod omap44xx_debugss_hwmod = {
486 .name = "debugss",
487 .class = &omap44xx_debugss_hwmod_class,
488 .clkdm_name = "emu_sys_clkdm",
489 .main_clk = "trace_clk_div_ck",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
493 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
494 },
495 },
496};
497
498/*
378 * 'dma' class 499 * 'dma' class
379 * dma controller for data exchange between memory to memory (i.e. internal or 500 * dma controller for data exchange between memory to memory (i.e. internal or
380 * external memory) and gp peripherals to memory or memory to gp peripherals 501 * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -816,6 +937,154 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
816}; 937};
817 938
818/* 939/*
940 * 'elm' class
941 * bch error location module
942 */
943
944static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
945 .rev_offs = 0x0000,
946 .sysc_offs = 0x0010,
947 .syss_offs = 0x0014,
948 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
949 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
950 SYSS_HAS_RESET_STATUS),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
952 .sysc_fields = &omap_hwmod_sysc_type1,
953};
954
955static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
956 .name = "elm",
957 .sysc = &omap44xx_elm_sysc,
958};
959
960/* elm */
961static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
962 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
963 { .irq = -1 }
964};
965
966static struct omap_hwmod omap44xx_elm_hwmod = {
967 .name = "elm",
968 .class = &omap44xx_elm_hwmod_class,
969 .clkdm_name = "l4_per_clkdm",
970 .mpu_irqs = omap44xx_elm_irqs,
971 .prcm = {
972 .omap4 = {
973 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
974 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
975 },
976 },
977};
978
979/*
980 * 'emif' class
981 * external memory interface no1
982 */
983
984static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
985 .rev_offs = 0x0000,
986};
987
988static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
989 .name = "emif",
990 .sysc = &omap44xx_emif_sysc,
991};
992
993/* emif1 */
994static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
995 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
996 { .irq = -1 }
997};
998
999static struct omap_hwmod omap44xx_emif1_hwmod = {
1000 .name = "emif1",
1001 .class = &omap44xx_emif_hwmod_class,
1002 .clkdm_name = "l3_emif_clkdm",
1003 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004 .mpu_irqs = omap44xx_emif1_irqs,
1005 .main_clk = "ddrphy_ck",
1006 .prcm = {
1007 .omap4 = {
1008 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1009 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1010 .modulemode = MODULEMODE_HWCTRL,
1011 },
1012 },
1013};
1014
1015/* emif2 */
1016static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1017 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1018 { .irq = -1 }
1019};
1020
1021static struct omap_hwmod omap44xx_emif2_hwmod = {
1022 .name = "emif2",
1023 .class = &omap44xx_emif_hwmod_class,
1024 .clkdm_name = "l3_emif_clkdm",
1025 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026 .mpu_irqs = omap44xx_emif2_irqs,
1027 .main_clk = "ddrphy_ck",
1028 .prcm = {
1029 .omap4 = {
1030 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1031 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1032 .modulemode = MODULEMODE_HWCTRL,
1033 },
1034 },
1035};
1036
1037/*
1038 * 'fdif' class
1039 * face detection hw accelerator module
1040 */
1041
1042static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1043 .rev_offs = 0x0000,
1044 .sysc_offs = 0x0010,
1045 /*
1046 * FDIF needs 100 OCP clk cycles delay after a softreset before
1047 * accessing sysconfig again.
1048 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050 *
1051 * TODO: Indicate errata when available.
1052 */
1053 .srst_udelay = 2,
1054 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058 .sysc_fields = &omap_hwmod_sysc_type2,
1059};
1060
1061static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1062 .name = "fdif",
1063 .sysc = &omap44xx_fdif_sysc,
1064};
1065
1066/* fdif */
1067static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1068 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1069 { .irq = -1 }
1070};
1071
1072static struct omap_hwmod omap44xx_fdif_hwmod = {
1073 .name = "fdif",
1074 .class = &omap44xx_fdif_hwmod_class,
1075 .clkdm_name = "iss_clkdm",
1076 .mpu_irqs = omap44xx_fdif_irqs,
1077 .main_clk = "fdif_fck",
1078 .prcm = {
1079 .omap4 = {
1080 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1082 .modulemode = MODULEMODE_SWCTRL,
1083 },
1084 },
1085};
1086
1087/*
819 * 'gpio' class 1088 * 'gpio' class
820 * general purpose io module 1089 * general purpose io module
821 */ 1090 */
@@ -1018,6 +1287,135 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
1018}; 1287};
1019 1288
1020/* 1289/*
1290 * 'gpmc' class
1291 * general purpose memory controller
1292 */
1293
1294static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1295 .rev_offs = 0x0000,
1296 .sysc_offs = 0x0010,
1297 .syss_offs = 0x0014,
1298 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1299 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1301 .sysc_fields = &omap_hwmod_sysc_type1,
1302};
1303
1304static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1305 .name = "gpmc",
1306 .sysc = &omap44xx_gpmc_sysc,
1307};
1308
1309/* gpmc */
1310static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1311 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1312 { .irq = -1 }
1313};
1314
1315static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1316 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1317 { .dma_req = -1 }
1318};
1319
1320static struct omap_hwmod omap44xx_gpmc_hwmod = {
1321 .name = "gpmc",
1322 .class = &omap44xx_gpmc_hwmod_class,
1323 .clkdm_name = "l3_2_clkdm",
1324 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1325 .mpu_irqs = omap44xx_gpmc_irqs,
1326 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1330 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_HWCTRL,
1332 },
1333 },
1334};
1335
1336/*
1337 * 'gpu' class
1338 * 2d/3d graphics accelerator
1339 */
1340
1341static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1342 .rev_offs = 0x1fc00,
1343 .sysc_offs = 0x1fc10,
1344 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1347 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1348 .sysc_fields = &omap_hwmod_sysc_type2,
1349};
1350
1351static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1352 .name = "gpu",
1353 .sysc = &omap44xx_gpu_sysc,
1354};
1355
1356/* gpu */
1357static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1358 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1359 { .irq = -1 }
1360};
1361
1362static struct omap_hwmod omap44xx_gpu_hwmod = {
1363 .name = "gpu",
1364 .class = &omap44xx_gpu_hwmod_class,
1365 .clkdm_name = "l3_gfx_clkdm",
1366 .mpu_irqs = omap44xx_gpu_irqs,
1367 .main_clk = "gpu_fck",
1368 .prcm = {
1369 .omap4 = {
1370 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1371 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1372 .modulemode = MODULEMODE_SWCTRL,
1373 },
1374 },
1375};
1376
1377/*
1378 * 'hdq1w' class
1379 * hdq / 1-wire serial interface controller
1380 */
1381
1382static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1383 .rev_offs = 0x0000,
1384 .sysc_offs = 0x0014,
1385 .syss_offs = 0x0018,
1386 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1387 SYSS_HAS_RESET_STATUS),
1388 .sysc_fields = &omap_hwmod_sysc_type1,
1389};
1390
1391static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1392 .name = "hdq1w",
1393 .sysc = &omap44xx_hdq1w_sysc,
1394};
1395
1396/* hdq1w */
1397static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1398 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1399 { .irq = -1 }
1400};
1401
1402static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1403 .name = "hdq1w",
1404 .class = &omap44xx_hdq1w_hwmod_class,
1405 .clkdm_name = "l4_per_clkdm",
1406 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1407 .mpu_irqs = omap44xx_hdq1w_irqs,
1408 .main_clk = "hdq1w_fck",
1409 .prcm = {
1410 .omap4 = {
1411 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1412 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1413 .modulemode = MODULEMODE_SWCTRL,
1414 },
1415 },
1416};
1417
1418/*
1021 * 'hsi' class 1419 * 'hsi' class
1022 * mipi high-speed synchronous serial interface (multichannel and full-duplex 1420 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1023 * serial if) 1421 * serial if)
@@ -1441,6 +1839,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
1441}; 1839};
1442 1840
1443/* 1841/*
1842 * 'mcasp' class
1843 * multi-channel audio serial port controller
1844 */
1845
1846/* The IP is not compliant to type1 / type2 scheme */
1847static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1848 .sidle_shift = 0,
1849};
1850
1851static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1852 .sysc_offs = 0x0004,
1853 .sysc_flags = SYSC_HAS_SIDLEMODE,
1854 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1855 SIDLE_SMART_WKUP),
1856 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1857};
1858
1859static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1860 .name = "mcasp",
1861 .sysc = &omap44xx_mcasp_sysc,
1862};
1863
1864/* mcasp */
1865static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1866 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1867 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1868 { .irq = -1 }
1869};
1870
1871static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1872 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1873 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1874 { .dma_req = -1 }
1875};
1876
1877static struct omap_hwmod omap44xx_mcasp_hwmod = {
1878 .name = "mcasp",
1879 .class = &omap44xx_mcasp_hwmod_class,
1880 .clkdm_name = "abe_clkdm",
1881 .mpu_irqs = omap44xx_mcasp_irqs,
1882 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1883 .main_clk = "mcasp_fck",
1884 .prcm = {
1885 .omap4 = {
1886 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1887 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1888 .modulemode = MODULEMODE_SWCTRL,
1889 },
1890 },
1891};
1892
1893/*
1444 * 'mcbsp' class 1894 * 'mcbsp' class
1445 * multi channel buffered serial port controller 1895 * multi channel buffered serial port controller
1446 */ 1896 */
@@ -2017,6 +2467,252 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
2017}; 2467};
2018 2468
2019/* 2469/*
2470 * 'ocmc_ram' class
2471 * top-level core on-chip ram
2472 */
2473
2474static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2475 .name = "ocmc_ram",
2476};
2477
2478/* ocmc_ram */
2479static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2480 .name = "ocmc_ram",
2481 .class = &omap44xx_ocmc_ram_hwmod_class,
2482 .clkdm_name = "l3_2_clkdm",
2483 .prcm = {
2484 .omap4 = {
2485 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2486 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2487 },
2488 },
2489};
2490
2491/*
2492 * 'ocp2scp' class
2493 * bridge to transform ocp interface protocol to scp (serial control port)
2494 * protocol
2495 */
2496
2497static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2498 .name = "ocp2scp",
2499};
2500
2501/* ocp2scp_usb_phy */
2502static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2503 { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2504};
2505
2506static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2507 .name = "ocp2scp_usb_phy",
2508 .class = &omap44xx_ocp2scp_hwmod_class,
2509 .clkdm_name = "l3_init_clkdm",
2510 .prcm = {
2511 .omap4 = {
2512 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2513 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2514 .modulemode = MODULEMODE_HWCTRL,
2515 },
2516 },
2517 .opt_clks = ocp2scp_usb_phy_opt_clks,
2518 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2519};
2520
2521/*
2522 * 'prcm' class
2523 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2524 * + clock manager 1 (in always on power domain) + local prm in mpu
2525 */
2526
2527static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2528 .name = "prcm",
2529};
2530
2531/* prcm_mpu */
2532static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2533 .name = "prcm_mpu",
2534 .class = &omap44xx_prcm_hwmod_class,
2535 .clkdm_name = "l4_wkup_clkdm",
2536};
2537
2538/* cm_core_aon */
2539static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2540 .name = "cm_core_aon",
2541 .class = &omap44xx_prcm_hwmod_class,
2542 .clkdm_name = "cm_clkdm",
2543};
2544
2545/* cm_core */
2546static struct omap_hwmod omap44xx_cm_core_hwmod = {
2547 .name = "cm_core",
2548 .class = &omap44xx_prcm_hwmod_class,
2549 .clkdm_name = "cm_clkdm",
2550};
2551
2552/* prm */
2553static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2554 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2555 { .irq = -1 }
2556};
2557
2558static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2559 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2560 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2561};
2562
2563static struct omap_hwmod omap44xx_prm_hwmod = {
2564 .name = "prm",
2565 .class = &omap44xx_prcm_hwmod_class,
2566 .clkdm_name = "prm_clkdm",
2567 .mpu_irqs = omap44xx_prm_irqs,
2568 .rst_lines = omap44xx_prm_resets,
2569 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2570};
2571
2572/*
2573 * 'scrm' class
2574 * system clock and reset manager
2575 */
2576
2577static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2578 .name = "scrm",
2579};
2580
2581/* scrm */
2582static struct omap_hwmod omap44xx_scrm_hwmod = {
2583 .name = "scrm",
2584 .class = &omap44xx_scrm_hwmod_class,
2585 .clkdm_name = "l4_wkup_clkdm",
2586};
2587
2588/*
2589 * 'sl2if' class
2590 * shared level 2 memory interface
2591 */
2592
2593static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2594 .name = "sl2if",
2595};
2596
2597/* sl2if */
2598static struct omap_hwmod omap44xx_sl2if_hwmod = {
2599 .name = "sl2if",
2600 .class = &omap44xx_sl2if_hwmod_class,
2601 .clkdm_name = "ivahd_clkdm",
2602 .prcm = {
2603 .omap4 = {
2604 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2605 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2606 .modulemode = MODULEMODE_HWCTRL,
2607 },
2608 },
2609};
2610
2611/*
2612 * 'slimbus' class
2613 * bidirectional, multi-drop, multi-channel two-line serial interface between
2614 * the device and external components
2615 */
2616
2617static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2618 .rev_offs = 0x0000,
2619 .sysc_offs = 0x0010,
2620 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2621 SYSC_HAS_SOFTRESET),
2622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2623 SIDLE_SMART_WKUP),
2624 .sysc_fields = &omap_hwmod_sysc_type2,
2625};
2626
2627static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2628 .name = "slimbus",
2629 .sysc = &omap44xx_slimbus_sysc,
2630};
2631
2632/* slimbus1 */
2633static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2634 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2635 { .irq = -1 }
2636};
2637
2638static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2639 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2640 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2641 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2642 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2643 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2644 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2645 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2646 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2647 { .dma_req = -1 }
2648};
2649
2650static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2651 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2652 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2653 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2654 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2655};
2656
2657static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2658 .name = "slimbus1",
2659 .class = &omap44xx_slimbus_hwmod_class,
2660 .clkdm_name = "abe_clkdm",
2661 .mpu_irqs = omap44xx_slimbus1_irqs,
2662 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2663 .prcm = {
2664 .omap4 = {
2665 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2666 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_SWCTRL,
2668 },
2669 },
2670 .opt_clks = slimbus1_opt_clks,
2671 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2672};
2673
2674/* slimbus2 */
2675static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2676 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2677 { .irq = -1 }
2678};
2679
2680static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2681 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2682 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2683 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2684 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2685 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2686 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2687 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2688 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2689 { .dma_req = -1 }
2690};
2691
2692static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2693 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2694 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2695 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2696};
2697
2698static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2699 .name = "slimbus2",
2700 .class = &omap44xx_slimbus_hwmod_class,
2701 .clkdm_name = "l4_per_clkdm",
2702 .mpu_irqs = omap44xx_slimbus2_irqs,
2703 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2704 .prcm = {
2705 .omap4 = {
2706 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2707 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2708 .modulemode = MODULEMODE_SWCTRL,
2709 },
2710 },
2711 .opt_clks = slimbus2_opt_clks,
2712 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2713};
2714
2715/*
2020 * 'smartreflex' class 2716 * 'smartreflex' class
2021 * smartreflex module (monitor silicon performance and outputs a measure of 2717 * smartreflex module (monitor silicon performance and outputs a measure of
2022 * performance error) 2718 * performance error)
@@ -2584,6 +3280,55 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
2584}; 3280};
2585 3281
2586/* 3282/*
3283 * 'usb_host_fs' class
3284 * full-speed usb host controller
3285 */
3286
3287/* The IP is not compliant to type1 / type2 scheme */
3288static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3289 .midle_shift = 4,
3290 .sidle_shift = 2,
3291 .srst_shift = 1,
3292};
3293
3294static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3295 .rev_offs = 0x0000,
3296 .sysc_offs = 0x0210,
3297 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3298 SYSC_HAS_SOFTRESET),
3299 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3300 SIDLE_SMART_WKUP),
3301 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3302};
3303
3304static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3305 .name = "usb_host_fs",
3306 .sysc = &omap44xx_usb_host_fs_sysc,
3307};
3308
3309/* usb_host_fs */
3310static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3311 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3312 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3313 { .irq = -1 }
3314};
3315
3316static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3317 .name = "usb_host_fs",
3318 .class = &omap44xx_usb_host_fs_hwmod_class,
3319 .clkdm_name = "l3_init_clkdm",
3320 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3321 .main_clk = "usb_host_fs_fck",
3322 .prcm = {
3323 .omap4 = {
3324 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3325 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3326 .modulemode = MODULEMODE_SWCTRL,
3327 },
3328 },
3329};
3330
3331/*
2587 * 'usb_host_hs' class 3332 * 'usb_host_hs' class
2588 * high-speed multi-port usb host controller 3333 * high-speed multi-port usb host controller
2589 */ 3334 */
@@ -2838,6 +3583,32 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2838 * interfaces 3583 * interfaces
2839 */ 3584 */
2840 3585
3586static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3587 {
3588 .pa_start = 0x4a204000,
3589 .pa_end = 0x4a2040ff,
3590 .flags = ADDR_TYPE_RT
3591 },
3592 { }
3593};
3594
3595/* c2c -> c2c_target_fw */
3596static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3597 .master = &omap44xx_c2c_hwmod,
3598 .slave = &omap44xx_c2c_target_fw_hwmod,
3599 .clk = "div_core_ck",
3600 .addr = omap44xx_c2c_target_fw_addrs,
3601 .user = OCP_USER_MPU,
3602};
3603
3604/* l4_cfg -> c2c_target_fw */
3605static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3606 .master = &omap44xx_l4_cfg_hwmod,
3607 .slave = &omap44xx_c2c_target_fw_hwmod,
3608 .clk = "l4_div_ck",
3609 .user = OCP_USER_MPU | OCP_USER_SDMA,
3610};
3611
2841/* l3_main_1 -> dmm */ 3612/* l3_main_1 -> dmm */
2842static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 3613static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2843 .master = &omap44xx_l3_main_1_hwmod, 3614 .master = &omap44xx_l3_main_1_hwmod,
@@ -2864,6 +3635,14 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2864 .user = OCP_USER_MPU, 3635 .user = OCP_USER_MPU,
2865}; 3636};
2866 3637
3638/* c2c -> emif_fw */
3639static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3640 .master = &omap44xx_c2c_hwmod,
3641 .slave = &omap44xx_emif_fw_hwmod,
3642 .clk = "div_core_ck",
3643 .user = OCP_USER_MPU | OCP_USER_SDMA,
3644};
3645
2867/* dmm -> emif_fw */ 3646/* dmm -> emif_fw */
2868static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 3647static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
2869 .master = &omap44xx_dmm_hwmod, 3648 .master = &omap44xx_dmm_hwmod,
@@ -2906,6 +3685,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2906 .user = OCP_USER_MPU | OCP_USER_SDMA, 3685 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907}; 3686};
2908 3687
3688/* ocp_wp_noc -> l3_instr */
3689static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3690 .master = &omap44xx_ocp_wp_noc_hwmod,
3691 .slave = &omap44xx_l3_instr_hwmod,
3692 .clk = "l3_div_ck",
3693 .user = OCP_USER_MPU | OCP_USER_SDMA,
3694};
3695
2909/* dsp -> l3_main_1 */ 3696/* dsp -> l3_main_1 */
2910static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { 3697static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2911 .master = &omap44xx_dsp_hwmod, 3698 .master = &omap44xx_dsp_hwmod,
@@ -2972,6 +3759,22 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2972 .user = OCP_USER_MPU, 3759 .user = OCP_USER_MPU,
2973}; 3760};
2974 3761
3762/* c2c_target_fw -> l3_main_2 */
3763static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3764 .master = &omap44xx_c2c_target_fw_hwmod,
3765 .slave = &omap44xx_l3_main_2_hwmod,
3766 .clk = "l3_div_ck",
3767 .user = OCP_USER_MPU | OCP_USER_SDMA,
3768};
3769
3770/* debugss -> l3_main_2 */
3771static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3772 .master = &omap44xx_debugss_hwmod,
3773 .slave = &omap44xx_l3_main_2_hwmod,
3774 .clk = "dbgclk_mux_ck",
3775 .user = OCP_USER_MPU | OCP_USER_SDMA,
3776};
3777
2975/* dma_system -> l3_main_2 */ 3778/* dma_system -> l3_main_2 */
2976static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { 3779static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2977 .master = &omap44xx_dma_system_hwmod, 3780 .master = &omap44xx_dma_system_hwmod,
@@ -2980,6 +3783,22 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2980 .user = OCP_USER_MPU | OCP_USER_SDMA, 3783 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981}; 3784};
2982 3785
3786/* fdif -> l3_main_2 */
3787static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3788 .master = &omap44xx_fdif_hwmod,
3789 .slave = &omap44xx_l3_main_2_hwmod,
3790 .clk = "l3_div_ck",
3791 .user = OCP_USER_MPU | OCP_USER_SDMA,
3792};
3793
3794/* gpu -> l3_main_2 */
3795static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3796 .master = &omap44xx_gpu_hwmod,
3797 .slave = &omap44xx_l3_main_2_hwmod,
3798 .clk = "l3_div_ck",
3799 .user = OCP_USER_MPU | OCP_USER_SDMA,
3800};
3801
2983/* hsi -> l3_main_2 */ 3802/* hsi -> l3_main_2 */
2984static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { 3803static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2985 .master = &omap44xx_hsi_hwmod, 3804 .master = &omap44xx_hsi_hwmod,
@@ -3038,6 +3857,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3038 .user = OCP_USER_MPU | OCP_USER_SDMA, 3857 .user = OCP_USER_MPU | OCP_USER_SDMA,
3039}; 3858};
3040 3859
3860/* usb_host_fs -> l3_main_2 */
3861static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3862 .master = &omap44xx_usb_host_fs_hwmod,
3863 .slave = &omap44xx_l3_main_2_hwmod,
3864 .clk = "l3_div_ck",
3865 .user = OCP_USER_MPU | OCP_USER_SDMA,
3866};
3867
3041/* usb_host_hs -> l3_main_2 */ 3868/* usb_host_hs -> l3_main_2 */
3042static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { 3869static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3043 .master = &omap44xx_usb_host_hs_hwmod, 3870 .master = &omap44xx_usb_host_hs_hwmod,
@@ -3152,6 +3979,24 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3152 .user = OCP_USER_MPU | OCP_USER_SDMA, 3979 .user = OCP_USER_MPU | OCP_USER_SDMA,
3153}; 3980};
3154 3981
3982static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3983 {
3984 .pa_start = 0x4a102000,
3985 .pa_end = 0x4a10207f,
3986 .flags = ADDR_TYPE_RT
3987 },
3988 { }
3989};
3990
3991/* l4_cfg -> ocp_wp_noc */
3992static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3993 .master = &omap44xx_l4_cfg_hwmod,
3994 .slave = &omap44xx_ocp_wp_noc_hwmod,
3995 .clk = "l4_div_ck",
3996 .addr = omap44xx_ocp_wp_noc_addrs,
3997 .user = OCP_USER_MPU | OCP_USER_SDMA,
3998};
3999
3155static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { 4000static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3156 { 4001 {
3157 .pa_start = 0x401f1000, 4002 .pa_start = 0x401f1000,
@@ -3188,6 +4033,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
3188 .user = OCP_USER_SDMA, 4033 .user = OCP_USER_SDMA,
3189}; 4034};
3190 4035
4036/* l3_main_2 -> c2c */
4037static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4038 .master = &omap44xx_l3_main_2_hwmod,
4039 .slave = &omap44xx_c2c_hwmod,
4040 .clk = "l3_div_ck",
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4042};
4043
3191static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { 4044static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
3192 { 4045 {
3193 .pa_start = 0x4a304000, 4046 .pa_start = 0x4a304000,
@@ -3206,6 +4059,96 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3206 .user = OCP_USER_MPU | OCP_USER_SDMA, 4059 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207}; 4060};
3208 4061
4062static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4063 {
4064 .pa_start = 0x4a002000,
4065 .pa_end = 0x4a0027ff,
4066 .flags = ADDR_TYPE_RT
4067 },
4068 { }
4069};
4070
4071/* l4_cfg -> ctrl_module_core */
4072static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4073 .master = &omap44xx_l4_cfg_hwmod,
4074 .slave = &omap44xx_ctrl_module_core_hwmod,
4075 .clk = "l4_div_ck",
4076 .addr = omap44xx_ctrl_module_core_addrs,
4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
4078};
4079
4080static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4081 {
4082 .pa_start = 0x4a100000,
4083 .pa_end = 0x4a1007ff,
4084 .flags = ADDR_TYPE_RT
4085 },
4086 { }
4087};
4088
4089/* l4_cfg -> ctrl_module_pad_core */
4090static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4091 .master = &omap44xx_l4_cfg_hwmod,
4092 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4093 .clk = "l4_div_ck",
4094 .addr = omap44xx_ctrl_module_pad_core_addrs,
4095 .user = OCP_USER_MPU | OCP_USER_SDMA,
4096};
4097
4098static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4099 {
4100 .pa_start = 0x4a30c000,
4101 .pa_end = 0x4a30c7ff,
4102 .flags = ADDR_TYPE_RT
4103 },
4104 { }
4105};
4106
4107/* l4_wkup -> ctrl_module_wkup */
4108static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4109 .master = &omap44xx_l4_wkup_hwmod,
4110 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4111 .clk = "l4_wkup_clk_mux_ck",
4112 .addr = omap44xx_ctrl_module_wkup_addrs,
4113 .user = OCP_USER_MPU | OCP_USER_SDMA,
4114};
4115
4116static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4117 {
4118 .pa_start = 0x4a31e000,
4119 .pa_end = 0x4a31e7ff,
4120 .flags = ADDR_TYPE_RT
4121 },
4122 { }
4123};
4124
4125/* l4_wkup -> ctrl_module_pad_wkup */
4126static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4127 .master = &omap44xx_l4_wkup_hwmod,
4128 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4129 .clk = "l4_wkup_clk_mux_ck",
4130 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4131 .user = OCP_USER_MPU | OCP_USER_SDMA,
4132};
4133
4134static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4135 {
4136 .pa_start = 0x54160000,
4137 .pa_end = 0x54167fff,
4138 .flags = ADDR_TYPE_RT
4139 },
4140 { }
4141};
4142
4143/* l3_instr -> debugss */
4144static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4145 .master = &omap44xx_l3_instr_hwmod,
4146 .slave = &omap44xx_debugss_hwmod,
4147 .clk = "l3_div_ck",
4148 .addr = omap44xx_debugss_addrs,
4149 .user = OCP_USER_MPU | OCP_USER_SDMA,
4150};
4151
3209static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { 4152static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3210 { 4153 {
3211 .pa_start = 0x4a056000, 4154 .pa_start = 0x4a056000,
@@ -3270,6 +4213,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3270 .user = OCP_USER_DSP, 4213 .user = OCP_USER_DSP,
3271}; 4214};
3272 4215
4216/* dsp -> sl2if */
4217static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4218 .master = &omap44xx_dsp_hwmod,
4219 .slave = &omap44xx_sl2if_hwmod,
4220 .clk = "dpll_iva_m5x2_ck",
4221 .user = OCP_USER_DSP,
4222};
4223
3273/* l4_cfg -> dsp */ 4224/* l4_cfg -> dsp */
3274static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { 4225static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3275 .master = &omap44xx_l4_cfg_hwmod, 4226 .master = &omap44xx_l4_cfg_hwmod,
@@ -3530,6 +4481,78 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3530 .user = OCP_USER_MPU, 4481 .user = OCP_USER_MPU,
3531}; 4482};
3532 4483
4484static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4485 {
4486 .pa_start = 0x48078000,
4487 .pa_end = 0x48078fff,
4488 .flags = ADDR_TYPE_RT
4489 },
4490 { }
4491};
4492
4493/* l4_per -> elm */
4494static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4495 .master = &omap44xx_l4_per_hwmod,
4496 .slave = &omap44xx_elm_hwmod,
4497 .clk = "l4_div_ck",
4498 .addr = omap44xx_elm_addrs,
4499 .user = OCP_USER_MPU | OCP_USER_SDMA,
4500};
4501
4502static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4503 {
4504 .pa_start = 0x4c000000,
4505 .pa_end = 0x4c0000ff,
4506 .flags = ADDR_TYPE_RT
4507 },
4508 { }
4509};
4510
4511/* emif_fw -> emif1 */
4512static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4513 .master = &omap44xx_emif_fw_hwmod,
4514 .slave = &omap44xx_emif1_hwmod,
4515 .clk = "l3_div_ck",
4516 .addr = omap44xx_emif1_addrs,
4517 .user = OCP_USER_MPU | OCP_USER_SDMA,
4518};
4519
4520static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4521 {
4522 .pa_start = 0x4d000000,
4523 .pa_end = 0x4d0000ff,
4524 .flags = ADDR_TYPE_RT
4525 },
4526 { }
4527};
4528
4529/* emif_fw -> emif2 */
4530static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4531 .master = &omap44xx_emif_fw_hwmod,
4532 .slave = &omap44xx_emif2_hwmod,
4533 .clk = "l3_div_ck",
4534 .addr = omap44xx_emif2_addrs,
4535 .user = OCP_USER_MPU | OCP_USER_SDMA,
4536};
4537
4538static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4539 {
4540 .pa_start = 0x4a10a000,
4541 .pa_end = 0x4a10a1ff,
4542 .flags = ADDR_TYPE_RT
4543 },
4544 { }
4545};
4546
4547/* l4_cfg -> fdif */
4548static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4549 .master = &omap44xx_l4_cfg_hwmod,
4550 .slave = &omap44xx_fdif_hwmod,
4551 .clk = "l4_div_ck",
4552 .addr = omap44xx_fdif_addrs,
4553 .user = OCP_USER_MPU | OCP_USER_SDMA,
4554};
4555
3533static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 4556static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
3534 { 4557 {
3535 .pa_start = 0x4a310000, 4558 .pa_start = 0x4a310000,
@@ -3638,6 +4661,60 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3638 .user = OCP_USER_MPU | OCP_USER_SDMA, 4661 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639}; 4662};
3640 4663
4664static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4665 {
4666 .pa_start = 0x50000000,
4667 .pa_end = 0x500003ff,
4668 .flags = ADDR_TYPE_RT
4669 },
4670 { }
4671};
4672
4673/* l3_main_2 -> gpmc */
4674static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4675 .master = &omap44xx_l3_main_2_hwmod,
4676 .slave = &omap44xx_gpmc_hwmod,
4677 .clk = "l3_div_ck",
4678 .addr = omap44xx_gpmc_addrs,
4679 .user = OCP_USER_MPU | OCP_USER_SDMA,
4680};
4681
4682static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4683 {
4684 .pa_start = 0x56000000,
4685 .pa_end = 0x5600ffff,
4686 .flags = ADDR_TYPE_RT
4687 },
4688 { }
4689};
4690
4691/* l3_main_2 -> gpu */
4692static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4693 .master = &omap44xx_l3_main_2_hwmod,
4694 .slave = &omap44xx_gpu_hwmod,
4695 .clk = "l3_div_ck",
4696 .addr = omap44xx_gpu_addrs,
4697 .user = OCP_USER_MPU | OCP_USER_SDMA,
4698};
4699
4700static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4701 {
4702 .pa_start = 0x480b2000,
4703 .pa_end = 0x480b201f,
4704 .flags = ADDR_TYPE_RT
4705 },
4706 { }
4707};
4708
4709/* l4_per -> hdq1w */
4710static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4711 .master = &omap44xx_l4_per_hwmod,
4712 .slave = &omap44xx_hdq1w_hwmod,
4713 .clk = "l4_div_ck",
4714 .addr = omap44xx_hdq1w_addrs,
4715 .user = OCP_USER_MPU | OCP_USER_SDMA,
4716};
4717
3641static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { 4718static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
3642 { 4719 {
3643 .pa_start = 0x4a058000, 4720 .pa_start = 0x4a058000,
@@ -3754,6 +4831,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
3754 .user = OCP_USER_MPU | OCP_USER_SDMA, 4831 .user = OCP_USER_MPU | OCP_USER_SDMA,
3755}; 4832};
3756 4833
4834/* iva -> sl2if */
4835static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4836 .master = &omap44xx_iva_hwmod,
4837 .slave = &omap44xx_sl2if_hwmod,
4838 .clk = "dpll_iva_m5x2_ck",
4839 .user = OCP_USER_IVA,
4840};
4841
3757static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { 4842static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
3758 { 4843 {
3759 .pa_start = 0x5a000000, 4844 .pa_start = 0x5a000000,
@@ -3808,6 +4893,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3808 .user = OCP_USER_MPU | OCP_USER_SDMA, 4893 .user = OCP_USER_MPU | OCP_USER_SDMA,
3809}; 4894};
3810 4895
4896static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4897 {
4898 .pa_start = 0x40128000,
4899 .pa_end = 0x401283ff,
4900 .flags = ADDR_TYPE_RT
4901 },
4902 { }
4903};
4904
4905/* l4_abe -> mcasp */
4906static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4907 .master = &omap44xx_l4_abe_hwmod,
4908 .slave = &omap44xx_mcasp_hwmod,
4909 .clk = "ocp_abe_iclk",
4910 .addr = omap44xx_mcasp_addrs,
4911 .user = OCP_USER_MPU,
4912};
4913
4914static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4915 {
4916 .pa_start = 0x49028000,
4917 .pa_end = 0x490283ff,
4918 .flags = ADDR_TYPE_RT
4919 },
4920 { }
4921};
4922
4923/* l4_abe -> mcasp (dma) */
4924static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4925 .master = &omap44xx_l4_abe_hwmod,
4926 .slave = &omap44xx_mcasp_hwmod,
4927 .clk = "ocp_abe_iclk",
4928 .addr = omap44xx_mcasp_dma_addrs,
4929 .user = OCP_USER_SDMA,
4930};
4931
3811static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 4932static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
3812 { 4933 {
3813 .name = "mpu", 4934 .name = "mpu",
@@ -4138,6 +5259,174 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4138 .user = OCP_USER_MPU | OCP_USER_SDMA, 5259 .user = OCP_USER_MPU | OCP_USER_SDMA,
4139}; 5260};
4140 5261
5262/* l3_main_2 -> ocmc_ram */
5263static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5264 .master = &omap44xx_l3_main_2_hwmod,
5265 .slave = &omap44xx_ocmc_ram_hwmod,
5266 .clk = "l3_div_ck",
5267 .user = OCP_USER_MPU | OCP_USER_SDMA,
5268};
5269
5270/* l4_cfg -> ocp2scp_usb_phy */
5271static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5272 .master = &omap44xx_l4_cfg_hwmod,
5273 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5274 .clk = "l4_div_ck",
5275 .user = OCP_USER_MPU | OCP_USER_SDMA,
5276};
5277
5278static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5279 {
5280 .pa_start = 0x48243000,
5281 .pa_end = 0x48243fff,
5282 .flags = ADDR_TYPE_RT
5283 },
5284 { }
5285};
5286
5287/* mpu_private -> prcm_mpu */
5288static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5289 .master = &omap44xx_mpu_private_hwmod,
5290 .slave = &omap44xx_prcm_mpu_hwmod,
5291 .clk = "l3_div_ck",
5292 .addr = omap44xx_prcm_mpu_addrs,
5293 .user = OCP_USER_MPU | OCP_USER_SDMA,
5294};
5295
5296static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5297 {
5298 .pa_start = 0x4a004000,
5299 .pa_end = 0x4a004fff,
5300 .flags = ADDR_TYPE_RT
5301 },
5302 { }
5303};
5304
5305/* l4_wkup -> cm_core_aon */
5306static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5307 .master = &omap44xx_l4_wkup_hwmod,
5308 .slave = &omap44xx_cm_core_aon_hwmod,
5309 .clk = "l4_wkup_clk_mux_ck",
5310 .addr = omap44xx_cm_core_aon_addrs,
5311 .user = OCP_USER_MPU | OCP_USER_SDMA,
5312};
5313
5314static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5315 {
5316 .pa_start = 0x4a008000,
5317 .pa_end = 0x4a009fff,
5318 .flags = ADDR_TYPE_RT
5319 },
5320 { }
5321};
5322
5323/* l4_cfg -> cm_core */
5324static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5325 .master = &omap44xx_l4_cfg_hwmod,
5326 .slave = &omap44xx_cm_core_hwmod,
5327 .clk = "l4_div_ck",
5328 .addr = omap44xx_cm_core_addrs,
5329 .user = OCP_USER_MPU | OCP_USER_SDMA,
5330};
5331
5332static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5333 {
5334 .pa_start = 0x4a306000,
5335 .pa_end = 0x4a307fff,
5336 .flags = ADDR_TYPE_RT
5337 },
5338 { }
5339};
5340
5341/* l4_wkup -> prm */
5342static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5343 .master = &omap44xx_l4_wkup_hwmod,
5344 .slave = &omap44xx_prm_hwmod,
5345 .clk = "l4_wkup_clk_mux_ck",
5346 .addr = omap44xx_prm_addrs,
5347 .user = OCP_USER_MPU | OCP_USER_SDMA,
5348};
5349
5350static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5351 {
5352 .pa_start = 0x4a30a000,
5353 .pa_end = 0x4a30a7ff,
5354 .flags = ADDR_TYPE_RT
5355 },
5356 { }
5357};
5358
5359/* l4_wkup -> scrm */
5360static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5361 .master = &omap44xx_l4_wkup_hwmod,
5362 .slave = &omap44xx_scrm_hwmod,
5363 .clk = "l4_wkup_clk_mux_ck",
5364 .addr = omap44xx_scrm_addrs,
5365 .user = OCP_USER_MPU | OCP_USER_SDMA,
5366};
5367
5368/* l3_main_2 -> sl2if */
5369static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5370 .master = &omap44xx_l3_main_2_hwmod,
5371 .slave = &omap44xx_sl2if_hwmod,
5372 .clk = "l3_div_ck",
5373 .user = OCP_USER_MPU | OCP_USER_SDMA,
5374};
5375
5376static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5377 {
5378 .pa_start = 0x4012c000,
5379 .pa_end = 0x4012c3ff,
5380 .flags = ADDR_TYPE_RT
5381 },
5382 { }
5383};
5384
5385/* l4_abe -> slimbus1 */
5386static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5387 .master = &omap44xx_l4_abe_hwmod,
5388 .slave = &omap44xx_slimbus1_hwmod,
5389 .clk = "ocp_abe_iclk",
5390 .addr = omap44xx_slimbus1_addrs,
5391 .user = OCP_USER_MPU,
5392};
5393
5394static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5395 {
5396 .pa_start = 0x4902c000,
5397 .pa_end = 0x4902c3ff,
5398 .flags = ADDR_TYPE_RT
5399 },
5400 { }
5401};
5402
5403/* l4_abe -> slimbus1 (dma) */
5404static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5405 .master = &omap44xx_l4_abe_hwmod,
5406 .slave = &omap44xx_slimbus1_hwmod,
5407 .clk = "ocp_abe_iclk",
5408 .addr = omap44xx_slimbus1_dma_addrs,
5409 .user = OCP_USER_SDMA,
5410};
5411
5412static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5413 {
5414 .pa_start = 0x48076000,
5415 .pa_end = 0x480763ff,
5416 .flags = ADDR_TYPE_RT
5417 },
5418 { }
5419};
5420
5421/* l4_per -> slimbus2 */
5422static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5423 .master = &omap44xx_l4_per_hwmod,
5424 .slave = &omap44xx_slimbus2_hwmod,
5425 .clk = "l4_div_ck",
5426 .addr = omap44xx_slimbus2_addrs,
5427 .user = OCP_USER_MPU | OCP_USER_SDMA,
5428};
5429
4141static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { 5430static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4142 { 5431 {
4143 .pa_start = 0x4a0dd000, 5432 .pa_start = 0x4a0dd000,
@@ -4552,6 +5841,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4552 .user = OCP_USER_MPU | OCP_USER_SDMA, 5841 .user = OCP_USER_MPU | OCP_USER_SDMA,
4553}; 5842};
4554 5843
5844static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5845 {
5846 .pa_start = 0x4a0a9000,
5847 .pa_end = 0x4a0a93ff,
5848 .flags = ADDR_TYPE_RT
5849 },
5850 { }
5851};
5852
5853/* l4_cfg -> usb_host_fs */
5854static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5855 .master = &omap44xx_l4_cfg_hwmod,
5856 .slave = &omap44xx_usb_host_fs_hwmod,
5857 .clk = "l4_div_ck",
5858 .addr = omap44xx_usb_host_fs_addrs,
5859 .user = OCP_USER_MPU | OCP_USER_SDMA,
5860};
5861
4555static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { 5862static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
4556 { 5863 {
4557 .name = "uhh", 5864 .name = "uhh",
@@ -4673,12 +5980,16 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4673}; 5980};
4674 5981
4675static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { 5982static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5983 &omap44xx_c2c__c2c_target_fw,
5984 &omap44xx_l4_cfg__c2c_target_fw,
4676 &omap44xx_l3_main_1__dmm, 5985 &omap44xx_l3_main_1__dmm,
4677 &omap44xx_mpu__dmm, 5986 &omap44xx_mpu__dmm,
5987 &omap44xx_c2c__emif_fw,
4678 &omap44xx_dmm__emif_fw, 5988 &omap44xx_dmm__emif_fw,
4679 &omap44xx_l4_cfg__emif_fw, 5989 &omap44xx_l4_cfg__emif_fw,
4680 &omap44xx_iva__l3_instr, 5990 &omap44xx_iva__l3_instr,
4681 &omap44xx_l3_main_3__l3_instr, 5991 &omap44xx_l3_main_3__l3_instr,
5992 &omap44xx_ocp_wp_noc__l3_instr,
4682 &omap44xx_dsp__l3_main_1, 5993 &omap44xx_dsp__l3_main_1,
4683 &omap44xx_dss__l3_main_1, 5994 &omap44xx_dss__l3_main_1,
4684 &omap44xx_l3_main_2__l3_main_1, 5995 &omap44xx_l3_main_2__l3_main_1,
@@ -4686,13 +5997,18 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4686 &omap44xx_mmc1__l3_main_1, 5997 &omap44xx_mmc1__l3_main_1,
4687 &omap44xx_mmc2__l3_main_1, 5998 &omap44xx_mmc2__l3_main_1,
4688 &omap44xx_mpu__l3_main_1, 5999 &omap44xx_mpu__l3_main_1,
6000 &omap44xx_c2c_target_fw__l3_main_2,
6001 &omap44xx_debugss__l3_main_2,
4689 &omap44xx_dma_system__l3_main_2, 6002 &omap44xx_dma_system__l3_main_2,
6003 &omap44xx_fdif__l3_main_2,
6004 &omap44xx_gpu__l3_main_2,
4690 &omap44xx_hsi__l3_main_2, 6005 &omap44xx_hsi__l3_main_2,
4691 &omap44xx_ipu__l3_main_2, 6006 &omap44xx_ipu__l3_main_2,
4692 &omap44xx_iss__l3_main_2, 6007 &omap44xx_iss__l3_main_2,
4693 &omap44xx_iva__l3_main_2, 6008 &omap44xx_iva__l3_main_2,
4694 &omap44xx_l3_main_1__l3_main_2, 6009 &omap44xx_l3_main_1__l3_main_2,
4695 &omap44xx_l4_cfg__l3_main_2, 6010 &omap44xx_l4_cfg__l3_main_2,
6011 &omap44xx_usb_host_fs__l3_main_2,
4696 &omap44xx_usb_host_hs__l3_main_2, 6012 &omap44xx_usb_host_hs__l3_main_2,
4697 &omap44xx_usb_otg_hs__l3_main_2, 6013 &omap44xx_usb_otg_hs__l3_main_2,
4698 &omap44xx_l3_main_1__l3_main_3, 6014 &omap44xx_l3_main_1__l3_main_3,
@@ -4706,13 +6022,21 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4706 &omap44xx_l3_main_2__l4_per, 6022 &omap44xx_l3_main_2__l4_per,
4707 &omap44xx_l4_cfg__l4_wkup, 6023 &omap44xx_l4_cfg__l4_wkup,
4708 &omap44xx_mpu__mpu_private, 6024 &omap44xx_mpu__mpu_private,
6025 &omap44xx_l4_cfg__ocp_wp_noc,
4709 &omap44xx_l4_abe__aess, 6026 &omap44xx_l4_abe__aess,
4710 &omap44xx_l4_abe__aess_dma, 6027 &omap44xx_l4_abe__aess_dma,
6028 &omap44xx_l3_main_2__c2c,
4711 &omap44xx_l4_wkup__counter_32k, 6029 &omap44xx_l4_wkup__counter_32k,
6030 &omap44xx_l4_cfg__ctrl_module_core,
6031 &omap44xx_l4_cfg__ctrl_module_pad_core,
6032 &omap44xx_l4_wkup__ctrl_module_wkup,
6033 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6034 &omap44xx_l3_instr__debugss,
4712 &omap44xx_l4_cfg__dma_system, 6035 &omap44xx_l4_cfg__dma_system,
4713 &omap44xx_l4_abe__dmic, 6036 &omap44xx_l4_abe__dmic,
4714 &omap44xx_l4_abe__dmic_dma, 6037 &omap44xx_l4_abe__dmic_dma,
4715 &omap44xx_dsp__iva, 6038 &omap44xx_dsp__iva,
6039 &omap44xx_dsp__sl2if,
4716 &omap44xx_l4_cfg__dsp, 6040 &omap44xx_l4_cfg__dsp,
4717 &omap44xx_l3_main_2__dss, 6041 &omap44xx_l3_main_2__dss,
4718 &omap44xx_l4_per__dss, 6042 &omap44xx_l4_per__dss,
@@ -4728,12 +6052,19 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4728 &omap44xx_l4_per__dss_rfbi, 6052 &omap44xx_l4_per__dss_rfbi,
4729 &omap44xx_l3_main_2__dss_venc, 6053 &omap44xx_l3_main_2__dss_venc,
4730 &omap44xx_l4_per__dss_venc, 6054 &omap44xx_l4_per__dss_venc,
6055 &omap44xx_l4_per__elm,
6056 &omap44xx_emif_fw__emif1,
6057 &omap44xx_emif_fw__emif2,
6058 &omap44xx_l4_cfg__fdif,
4731 &omap44xx_l4_wkup__gpio1, 6059 &omap44xx_l4_wkup__gpio1,
4732 &omap44xx_l4_per__gpio2, 6060 &omap44xx_l4_per__gpio2,
4733 &omap44xx_l4_per__gpio3, 6061 &omap44xx_l4_per__gpio3,
4734 &omap44xx_l4_per__gpio4, 6062 &omap44xx_l4_per__gpio4,
4735 &omap44xx_l4_per__gpio5, 6063 &omap44xx_l4_per__gpio5,
4736 &omap44xx_l4_per__gpio6, 6064 &omap44xx_l4_per__gpio6,
6065 &omap44xx_l3_main_2__gpmc,
6066 &omap44xx_l3_main_2__gpu,
6067 &omap44xx_l4_per__hdq1w,
4737 &omap44xx_l4_cfg__hsi, 6068 &omap44xx_l4_cfg__hsi,
4738 &omap44xx_l4_per__i2c1, 6069 &omap44xx_l4_per__i2c1,
4739 &omap44xx_l4_per__i2c2, 6070 &omap44xx_l4_per__i2c2,
@@ -4741,9 +6072,12 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4741 &omap44xx_l4_per__i2c4, 6072 &omap44xx_l4_per__i2c4,
4742 &omap44xx_l3_main_2__ipu, 6073 &omap44xx_l3_main_2__ipu,
4743 &omap44xx_l3_main_2__iss, 6074 &omap44xx_l3_main_2__iss,
6075 &omap44xx_iva__sl2if,
4744 &omap44xx_l3_main_2__iva, 6076 &omap44xx_l3_main_2__iva,
4745 &omap44xx_l4_wkup__kbd, 6077 &omap44xx_l4_wkup__kbd,
4746 &omap44xx_l4_cfg__mailbox, 6078 &omap44xx_l4_cfg__mailbox,
6079 &omap44xx_l4_abe__mcasp,
6080 &omap44xx_l4_abe__mcasp_dma,
4747 &omap44xx_l4_abe__mcbsp1, 6081 &omap44xx_l4_abe__mcbsp1,
4748 &omap44xx_l4_abe__mcbsp1_dma, 6082 &omap44xx_l4_abe__mcbsp1_dma,
4749 &omap44xx_l4_abe__mcbsp2, 6083 &omap44xx_l4_abe__mcbsp2,
@@ -4762,6 +6096,17 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4762 &omap44xx_l4_per__mmc3, 6096 &omap44xx_l4_per__mmc3,
4763 &omap44xx_l4_per__mmc4, 6097 &omap44xx_l4_per__mmc4,
4764 &omap44xx_l4_per__mmc5, 6098 &omap44xx_l4_per__mmc5,
6099 &omap44xx_l3_main_2__ocmc_ram,
6100 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6101 &omap44xx_mpu_private__prcm_mpu,
6102 &omap44xx_l4_wkup__cm_core_aon,
6103 &omap44xx_l4_cfg__cm_core,
6104 &omap44xx_l4_wkup__prm,
6105 &omap44xx_l4_wkup__scrm,
6106 &omap44xx_l3_main_2__sl2if,
6107 &omap44xx_l4_abe__slimbus1,
6108 &omap44xx_l4_abe__slimbus1_dma,
6109 &omap44xx_l4_per__slimbus2,
4765 &omap44xx_l4_cfg__smartreflex_core, 6110 &omap44xx_l4_cfg__smartreflex_core,
4766 &omap44xx_l4_cfg__smartreflex_iva, 6111 &omap44xx_l4_cfg__smartreflex_iva,
4767 &omap44xx_l4_cfg__smartreflex_mpu, 6112 &omap44xx_l4_cfg__smartreflex_mpu,
@@ -4785,6 +6130,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4785 &omap44xx_l4_per__uart2, 6130 &omap44xx_l4_per__uart2,
4786 &omap44xx_l4_per__uart3, 6131 &omap44xx_l4_per__uart3,
4787 &omap44xx_l4_per__uart4, 6132 &omap44xx_l4_per__uart4,
6133 &omap44xx_l4_cfg__usb_host_fs,
4788 &omap44xx_l4_cfg__usb_host_hs, 6134 &omap44xx_l4_cfg__usb_host_hs,
4789 &omap44xx_l4_cfg__usb_otg_hs, 6135 &omap44xx_l4_cfg__usb_otg_hs,
4790 &omap44xx_l4_cfg__usb_tll_hs, 6136 &omap44xx_l4_cfg__usb_tll_hs,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 15:49:32 -0500