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authorThara Gopinath <thara@ti.com>2011-02-23 02:14:05 -0500
committerPaul Walmsley <paul@pwsan.com>2011-02-27 21:11:28 -0500
commitb6b582291fbe8cca987c8823c87ee4a62b24f105 (patch)
tree28f45e2976a737dfcc49645f9790ce79e2af4239 /arch/arm/mach-omap2/omap_hwmod_2430_data.c
parenteddb12624d9a8087f1f8f1a2812f840c5e8191ac (diff)
OMAP2430: hwmod data: add dmtimer
Add dmtimer data. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2430_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c633
1 files changed, 633 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index de0015d38433..c03699653b0b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -19,6 +19,7 @@
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h> 21#include <plat/mcspi.h>
22#include <plat/dmtimer.h>
22#include <plat/l3_2xxx.h> 23#include <plat/l3_2xxx.h>
23 24
24#include "omap_hwmod_common_data.h" 25#include "omap_hwmod_common_data.h"
@@ -393,6 +394,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
394}; 395};
395 396
397/* Timer Common */
398static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
399 .rev_offs = 0x0000,
400 .sysc_offs = 0x0010,
401 .syss_offs = 0x0014,
402 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
403 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
404 SYSC_HAS_AUTOIDLE),
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
406 .sysc_fields = &omap_hwmod_sysc_type1,
407};
408
409static struct omap_hwmod_class omap2430_timer_hwmod_class = {
410 .name = "timer",
411 .sysc = &omap2430_timer_sysc,
412 .rev = OMAP_TIMER_IP_VERSION_1,
413};
414
415/* timer1 */
416static struct omap_hwmod omap2430_timer1_hwmod;
417static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
418 { .irq = 37, },
419};
420
421static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
422 {
423 .pa_start = 0x49018000,
424 .pa_end = 0x49018000 + SZ_1K - 1,
425 .flags = ADDR_TYPE_RT
426 },
427};
428
429/* l4_wkup -> timer1 */
430static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
431 .master = &omap2430_l4_wkup_hwmod,
432 .slave = &omap2430_timer1_hwmod,
433 .clk = "gpt1_ick",
434 .addr = omap2430_timer1_addrs,
435 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
437};
438
439/* timer1 slave port */
440static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
441 &omap2430_l4_wkup__timer1,
442};
443
444/* timer1 hwmod */
445static struct omap_hwmod omap2430_timer1_hwmod = {
446 .name = "timer1",
447 .mpu_irqs = omap2430_timer1_mpu_irqs,
448 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
449 .main_clk = "gpt1_fck",
450 .prcm = {
451 .omap2 = {
452 .prcm_reg_id = 1,
453 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
454 .module_offs = WKUP_MOD,
455 .idlest_reg_id = 1,
456 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
457 },
458 },
459 .slaves = omap2430_timer1_slaves,
460 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
461 .class = &omap2430_timer_hwmod_class,
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
463};
464
465/* timer2 */
466static struct omap_hwmod omap2430_timer2_hwmod;
467static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
468 { .irq = 38, },
469};
470
471static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
472 {
473 .pa_start = 0x4802a000,
474 .pa_end = 0x4802a000 + SZ_1K - 1,
475 .flags = ADDR_TYPE_RT
476 },
477};
478
479/* l4_core -> timer2 */
480static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
481 .master = &omap2430_l4_core_hwmod,
482 .slave = &omap2430_timer2_hwmod,
483 .clk = "gpt2_ick",
484 .addr = omap2430_timer2_addrs,
485 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* timer2 slave port */
490static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
491 &omap2430_l4_core__timer2,
492};
493
494/* timer2 hwmod */
495static struct omap_hwmod omap2430_timer2_hwmod = {
496 .name = "timer2",
497 .mpu_irqs = omap2430_timer2_mpu_irqs,
498 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
499 .main_clk = "gpt2_fck",
500 .prcm = {
501 .omap2 = {
502 .prcm_reg_id = 1,
503 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
504 .module_offs = CORE_MOD,
505 .idlest_reg_id = 1,
506 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
507 },
508 },
509 .slaves = omap2430_timer2_slaves,
510 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
511 .class = &omap2430_timer_hwmod_class,
512 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
513};
514
515/* timer3 */
516static struct omap_hwmod omap2430_timer3_hwmod;
517static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
518 { .irq = 39, },
519};
520
521static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
522 {
523 .pa_start = 0x48078000,
524 .pa_end = 0x48078000 + SZ_1K - 1,
525 .flags = ADDR_TYPE_RT
526 },
527};
528
529/* l4_core -> timer3 */
530static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
531 .master = &omap2430_l4_core_hwmod,
532 .slave = &omap2430_timer3_hwmod,
533 .clk = "gpt3_ick",
534 .addr = omap2430_timer3_addrs,
535 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
536 .user = OCP_USER_MPU | OCP_USER_SDMA,
537};
538
539/* timer3 slave port */
540static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
541 &omap2430_l4_core__timer3,
542};
543
544/* timer3 hwmod */
545static struct omap_hwmod omap2430_timer3_hwmod = {
546 .name = "timer3",
547 .mpu_irqs = omap2430_timer3_mpu_irqs,
548 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
549 .main_clk = "gpt3_fck",
550 .prcm = {
551 .omap2 = {
552 .prcm_reg_id = 1,
553 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
554 .module_offs = CORE_MOD,
555 .idlest_reg_id = 1,
556 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
557 },
558 },
559 .slaves = omap2430_timer3_slaves,
560 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
561 .class = &omap2430_timer_hwmod_class,
562 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
563};
564
565/* timer4 */
566static struct omap_hwmod omap2430_timer4_hwmod;
567static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
568 { .irq = 40, },
569};
570
571static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
572 {
573 .pa_start = 0x4807a000,
574 .pa_end = 0x4807a000 + SZ_1K - 1,
575 .flags = ADDR_TYPE_RT
576 },
577};
578
579/* l4_core -> timer4 */
580static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
581 .master = &omap2430_l4_core_hwmod,
582 .slave = &omap2430_timer4_hwmod,
583 .clk = "gpt4_ick",
584 .addr = omap2430_timer4_addrs,
585 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
586 .user = OCP_USER_MPU | OCP_USER_SDMA,
587};
588
589/* timer4 slave port */
590static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
591 &omap2430_l4_core__timer4,
592};
593
594/* timer4 hwmod */
595static struct omap_hwmod omap2430_timer4_hwmod = {
596 .name = "timer4",
597 .mpu_irqs = omap2430_timer4_mpu_irqs,
598 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
599 .main_clk = "gpt4_fck",
600 .prcm = {
601 .omap2 = {
602 .prcm_reg_id = 1,
603 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
604 .module_offs = CORE_MOD,
605 .idlest_reg_id = 1,
606 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
607 },
608 },
609 .slaves = omap2430_timer4_slaves,
610 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
611 .class = &omap2430_timer_hwmod_class,
612 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
613};
614
615/* timer5 */
616static struct omap_hwmod omap2430_timer5_hwmod;
617static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
618 { .irq = 41, },
619};
620
621static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
622 {
623 .pa_start = 0x4807c000,
624 .pa_end = 0x4807c000 + SZ_1K - 1,
625 .flags = ADDR_TYPE_RT
626 },
627};
628
629/* l4_core -> timer5 */
630static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
631 .master = &omap2430_l4_core_hwmod,
632 .slave = &omap2430_timer5_hwmod,
633 .clk = "gpt5_ick",
634 .addr = omap2430_timer5_addrs,
635 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
636 .user = OCP_USER_MPU | OCP_USER_SDMA,
637};
638
639/* timer5 slave port */
640static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
641 &omap2430_l4_core__timer5,
642};
643
644/* timer5 hwmod */
645static struct omap_hwmod omap2430_timer5_hwmod = {
646 .name = "timer5",
647 .mpu_irqs = omap2430_timer5_mpu_irqs,
648 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
649 .main_clk = "gpt5_fck",
650 .prcm = {
651 .omap2 = {
652 .prcm_reg_id = 1,
653 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
654 .module_offs = CORE_MOD,
655 .idlest_reg_id = 1,
656 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
657 },
658 },
659 .slaves = omap2430_timer5_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
661 .class = &omap2430_timer_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
663};
664
665/* timer6 */
666static struct omap_hwmod omap2430_timer6_hwmod;
667static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
668 { .irq = 42, },
669};
670
671static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
672 {
673 .pa_start = 0x4807e000,
674 .pa_end = 0x4807e000 + SZ_1K - 1,
675 .flags = ADDR_TYPE_RT
676 },
677};
678
679/* l4_core -> timer6 */
680static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
681 .master = &omap2430_l4_core_hwmod,
682 .slave = &omap2430_timer6_hwmod,
683 .clk = "gpt6_ick",
684 .addr = omap2430_timer6_addrs,
685 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
686 .user = OCP_USER_MPU | OCP_USER_SDMA,
687};
688
689/* timer6 slave port */
690static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
691 &omap2430_l4_core__timer6,
692};
693
694/* timer6 hwmod */
695static struct omap_hwmod omap2430_timer6_hwmod = {
696 .name = "timer6",
697 .mpu_irqs = omap2430_timer6_mpu_irqs,
698 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
699 .main_clk = "gpt6_fck",
700 .prcm = {
701 .omap2 = {
702 .prcm_reg_id = 1,
703 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
704 .module_offs = CORE_MOD,
705 .idlest_reg_id = 1,
706 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
707 },
708 },
709 .slaves = omap2430_timer6_slaves,
710 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
711 .class = &omap2430_timer_hwmod_class,
712 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
713};
714
715/* timer7 */
716static struct omap_hwmod omap2430_timer7_hwmod;
717static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
718 { .irq = 43, },
719};
720
721static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
722 {
723 .pa_start = 0x48080000,
724 .pa_end = 0x48080000 + SZ_1K - 1,
725 .flags = ADDR_TYPE_RT
726 },
727};
728
729/* l4_core -> timer7 */
730static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
731 .master = &omap2430_l4_core_hwmod,
732 .slave = &omap2430_timer7_hwmod,
733 .clk = "gpt7_ick",
734 .addr = omap2430_timer7_addrs,
735 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
736 .user = OCP_USER_MPU | OCP_USER_SDMA,
737};
738
739/* timer7 slave port */
740static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
741 &omap2430_l4_core__timer7,
742};
743
744/* timer7 hwmod */
745static struct omap_hwmod omap2430_timer7_hwmod = {
746 .name = "timer7",
747 .mpu_irqs = omap2430_timer7_mpu_irqs,
748 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
749 .main_clk = "gpt7_fck",
750 .prcm = {
751 .omap2 = {
752 .prcm_reg_id = 1,
753 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
754 .module_offs = CORE_MOD,
755 .idlest_reg_id = 1,
756 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
757 },
758 },
759 .slaves = omap2430_timer7_slaves,
760 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
761 .class = &omap2430_timer_hwmod_class,
762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
763};
764
765/* timer8 */
766static struct omap_hwmod omap2430_timer8_hwmod;
767static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
768 { .irq = 44, },
769};
770
771static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
772 {
773 .pa_start = 0x48082000,
774 .pa_end = 0x48082000 + SZ_1K - 1,
775 .flags = ADDR_TYPE_RT
776 },
777};
778
779/* l4_core -> timer8 */
780static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
781 .master = &omap2430_l4_core_hwmod,
782 .slave = &omap2430_timer8_hwmod,
783 .clk = "gpt8_ick",
784 .addr = omap2430_timer8_addrs,
785 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
786 .user = OCP_USER_MPU | OCP_USER_SDMA,
787};
788
789/* timer8 slave port */
790static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
791 &omap2430_l4_core__timer8,
792};
793
794/* timer8 hwmod */
795static struct omap_hwmod omap2430_timer8_hwmod = {
796 .name = "timer8",
797 .mpu_irqs = omap2430_timer8_mpu_irqs,
798 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
799 .main_clk = "gpt8_fck",
800 .prcm = {
801 .omap2 = {
802 .prcm_reg_id = 1,
803 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
804 .module_offs = CORE_MOD,
805 .idlest_reg_id = 1,
806 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
807 },
808 },
809 .slaves = omap2430_timer8_slaves,
810 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
811 .class = &omap2430_timer_hwmod_class,
812 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
813};
814
815/* timer9 */
816static struct omap_hwmod omap2430_timer9_hwmod;
817static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
818 { .irq = 45, },
819};
820
821static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
822 {
823 .pa_start = 0x48084000,
824 .pa_end = 0x48084000 + SZ_1K - 1,
825 .flags = ADDR_TYPE_RT
826 },
827};
828
829/* l4_core -> timer9 */
830static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
831 .master = &omap2430_l4_core_hwmod,
832 .slave = &omap2430_timer9_hwmod,
833 .clk = "gpt9_ick",
834 .addr = omap2430_timer9_addrs,
835 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
837};
838
839/* timer9 slave port */
840static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
841 &omap2430_l4_core__timer9,
842};
843
844/* timer9 hwmod */
845static struct omap_hwmod omap2430_timer9_hwmod = {
846 .name = "timer9",
847 .mpu_irqs = omap2430_timer9_mpu_irqs,
848 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
849 .main_clk = "gpt9_fck",
850 .prcm = {
851 .omap2 = {
852 .prcm_reg_id = 1,
853 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
854 .module_offs = CORE_MOD,
855 .idlest_reg_id = 1,
856 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
857 },
858 },
859 .slaves = omap2430_timer9_slaves,
860 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
861 .class = &omap2430_timer_hwmod_class,
862 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
863};
864
865/* timer10 */
866static struct omap_hwmod omap2430_timer10_hwmod;
867static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
868 { .irq = 46, },
869};
870
871static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
872 {
873 .pa_start = 0x48086000,
874 .pa_end = 0x48086000 + SZ_1K - 1,
875 .flags = ADDR_TYPE_RT
876 },
877};
878
879/* l4_core -> timer10 */
880static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
881 .master = &omap2430_l4_core_hwmod,
882 .slave = &omap2430_timer10_hwmod,
883 .clk = "gpt10_ick",
884 .addr = omap2430_timer10_addrs,
885 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
886 .user = OCP_USER_MPU | OCP_USER_SDMA,
887};
888
889/* timer10 slave port */
890static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
891 &omap2430_l4_core__timer10,
892};
893
894/* timer10 hwmod */
895static struct omap_hwmod omap2430_timer10_hwmod = {
896 .name = "timer10",
897 .mpu_irqs = omap2430_timer10_mpu_irqs,
898 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
899 .main_clk = "gpt10_fck",
900 .prcm = {
901 .omap2 = {
902 .prcm_reg_id = 1,
903 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
904 .module_offs = CORE_MOD,
905 .idlest_reg_id = 1,
906 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
907 },
908 },
909 .slaves = omap2430_timer10_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
911 .class = &omap2430_timer_hwmod_class,
912 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
913};
914
915/* timer11 */
916static struct omap_hwmod omap2430_timer11_hwmod;
917static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
918 { .irq = 47, },
919};
920
921static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
922 {
923 .pa_start = 0x48088000,
924 .pa_end = 0x48088000 + SZ_1K - 1,
925 .flags = ADDR_TYPE_RT
926 },
927};
928
929/* l4_core -> timer11 */
930static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
931 .master = &omap2430_l4_core_hwmod,
932 .slave = &omap2430_timer11_hwmod,
933 .clk = "gpt11_ick",
934 .addr = omap2430_timer11_addrs,
935 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937};
938
939/* timer11 slave port */
940static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
941 &omap2430_l4_core__timer11,
942};
943
944/* timer11 hwmod */
945static struct omap_hwmod omap2430_timer11_hwmod = {
946 .name = "timer11",
947 .mpu_irqs = omap2430_timer11_mpu_irqs,
948 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
949 .main_clk = "gpt11_fck",
950 .prcm = {
951 .omap2 = {
952 .prcm_reg_id = 1,
953 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
954 .module_offs = CORE_MOD,
955 .idlest_reg_id = 1,
956 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
957 },
958 },
959 .slaves = omap2430_timer11_slaves,
960 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
961 .class = &omap2430_timer_hwmod_class,
962 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
963};
964
965/* timer12 */
966static struct omap_hwmod omap2430_timer12_hwmod;
967static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
968 { .irq = 48, },
969};
970
971static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
972 {
973 .pa_start = 0x4808a000,
974 .pa_end = 0x4808a000 + SZ_1K - 1,
975 .flags = ADDR_TYPE_RT
976 },
977};
978
979/* l4_core -> timer12 */
980static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
981 .master = &omap2430_l4_core_hwmod,
982 .slave = &omap2430_timer12_hwmod,
983 .clk = "gpt12_ick",
984 .addr = omap2430_timer12_addrs,
985 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
986 .user = OCP_USER_MPU | OCP_USER_SDMA,
987};
988
989/* timer12 slave port */
990static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
991 &omap2430_l4_core__timer12,
992};
993
994/* timer12 hwmod */
995static struct omap_hwmod omap2430_timer12_hwmod = {
996 .name = "timer12",
997 .mpu_irqs = omap2430_timer12_mpu_irqs,
998 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
999 .main_clk = "gpt12_fck",
1000 .prcm = {
1001 .omap2 = {
1002 .prcm_reg_id = 1,
1003 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1004 .module_offs = CORE_MOD,
1005 .idlest_reg_id = 1,
1006 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1007 },
1008 },
1009 .slaves = omap2430_timer12_slaves,
1010 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1011 .class = &omap2430_timer_hwmod_class,
1012 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1013};
1014
396/* l4_wkup -> wd_timer2 */ 1015/* l4_wkup -> wd_timer2 */
397static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 1016static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
398 { 1017 {
@@ -1514,6 +2133,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1514 &omap2430_l4_wkup_hwmod, 2133 &omap2430_l4_wkup_hwmod,
1515 &omap2430_mpu_hwmod, 2134 &omap2430_mpu_hwmod,
1516 &omap2430_iva_hwmod, 2135 &omap2430_iva_hwmod,
2136
2137 &omap2430_timer1_hwmod,
2138 &omap2430_timer2_hwmod,
2139 &omap2430_timer3_hwmod,
2140 &omap2430_timer4_hwmod,
2141 &omap2430_timer5_hwmod,
2142 &omap2430_timer6_hwmod,
2143 &omap2430_timer7_hwmod,
2144 &omap2430_timer8_hwmod,
2145 &omap2430_timer9_hwmod,
2146 &omap2430_timer10_hwmod,
2147 &omap2430_timer11_hwmod,
2148 &omap2430_timer12_hwmod,
2149
1517 &omap2430_wd_timer2_hwmod, 2150 &omap2430_wd_timer2_hwmod,
1518 &omap2430_uart1_hwmod, 2151 &omap2430_uart1_hwmod,
1519 &omap2430_uart2_hwmod, 2152 &omap2430_uart2_hwmod,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 23:38:01 -0500