diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 14:18:22 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:37 -0500 |
| commit | da0747d4faf55320f0f6cbcd8525e2a8e4619925 (patch) | |
| tree | b3fce6c33df8f555d9adbe00d679e48f9f4a81c0 /arch/arm/mach-omap2/cm-regbits-24xx.h | |
| parent | 027d8ded5d1c142eb120caff7a395c0637467ac9 (diff) | |
[ARM] OMAP2 PRCM: clean up CM_IDLEST bits
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly
marked as being OMAP2xxx-wide, when they were actually 2420-specific.
Also, originally when the PRCM register macros were defined, bit shift
macros used a "_SHIFT" suffix, and mask macros used none. This became
a source of bugs and confusion, as the mask macros were mistakenly
used for shift values. Gradually, the mask macros have been updated,
piece by piece, to add a "_MASK" suffix on the end to clarify. This
patch applies this change to the CM_IDLEST_* register bits.
The patch also adds a few bits that were missing, mostly from the 3430ES1
to ES2 revisions.
linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77,
e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of
9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-24xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 80 |
1 files changed, 53 insertions, 27 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 1098ecfab861..297a2fe634ea 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -110,35 +110,56 @@ | |||
| 110 | #define OMAP24XX_EN_DES (1 << 0) | 110 | #define OMAP24XX_EN_DES (1 << 0) |
| 111 | 111 | ||
| 112 | /* CM_IDLEST1_CORE specific bits */ | 112 | /* CM_IDLEST1_CORE specific bits */ |
| 113 | #define OMAP24XX_ST_MAILBOXES (1 << 30) | 113 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
| 114 | #define OMAP24XX_ST_WDT4 (1 << 29) | 114 | #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) |
| 115 | #define OMAP2420_ST_WDT3 (1 << 28) | 115 | #define OMAP24XX_ST_WDT4_SHIFT 29 |
| 116 | #define OMAP24XX_ST_MSPRO (1 << 27) | 116 | #define OMAP24XX_ST_WDT4_MASK (1 << 29) |
| 117 | #define OMAP24XX_ST_FAC (1 << 25) | 117 | #define OMAP2420_ST_WDT3_SHIFT 28 |
| 118 | #define OMAP2420_ST_EAC (1 << 24) | 118 | #define OMAP2420_ST_WDT3_MASK (1 << 28) |
| 119 | #define OMAP24XX_ST_HDQ (1 << 23) | 119 | #define OMAP24XX_ST_MSPRO_SHIFT 27 |
| 120 | #define OMAP24XX_ST_I2C2 (1 << 20) | 120 | #define OMAP24XX_ST_MSPRO_MASK (1 << 27) |
| 121 | #define OMAP24XX_ST_I2C1 (1 << 19) | 121 | #define OMAP24XX_ST_FAC_SHIFT 25 |
| 122 | #define OMAP24XX_ST_MCBSP2 (1 << 16) | 122 | #define OMAP24XX_ST_FAC_MASK (1 << 25) |
| 123 | #define OMAP24XX_ST_MCBSP1 (1 << 15) | 123 | #define OMAP2420_ST_EAC_SHIFT 24 |
| 124 | #define OMAP24XX_ST_DSS (1 << 0) | 124 | #define OMAP2420_ST_EAC_MASK (1 << 24) |
| 125 | #define OMAP24XX_ST_HDQ_SHIFT 23 | ||
| 126 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | ||
| 127 | #define OMAP2420_ST_I2C2_SHIFT 20 | ||
| 128 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | ||
| 129 | #define OMAP2420_ST_I2C1_SHIFT 19 | ||
| 130 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | ||
| 131 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | ||
| 132 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | ||
| 133 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | ||
| 134 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | ||
| 135 | #define OMAP24XX_ST_DSS_SHIFT 0 | ||
| 136 | #define OMAP24XX_ST_DSS_MASK (1 << 0) | ||
| 125 | 137 | ||
| 126 | /* CM_IDLEST2_CORE */ | 138 | /* CM_IDLEST2_CORE */ |
| 127 | #define OMAP2430_ST_MCBSP5 (1 << 5) | 139 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
| 128 | #define OMAP2430_ST_MCBSP4 (1 << 4) | 140 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) |
| 129 | #define OMAP2430_ST_MCBSP3 (1 << 3) | 141 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
| 130 | #define OMAP24XX_ST_SSI (1 << 1) | 142 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) |
| 143 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | ||
| 144 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | ||
| 145 | #define OMAP24XX_ST_SSI_SHIFT 1 | ||
| 146 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | ||
| 131 | 147 | ||
| 132 | /* CM_IDLEST3_CORE */ | 148 | /* CM_IDLEST3_CORE */ |
| 133 | /* 2430 only */ | 149 | /* 2430 only */ |
| 134 | #define OMAP2430_ST_SDRC (1 << 2) | 150 | #define OMAP2430_ST_SDRC_MASK (1 << 2) |
| 135 | 151 | ||
| 136 | /* CM_IDLEST4_CORE */ | 152 | /* CM_IDLEST4_CORE */ |
| 137 | #define OMAP24XX_ST_PKA (1 << 4) | 153 | #define OMAP24XX_ST_PKA_SHIFT 4 |
| 138 | #define OMAP24XX_ST_AES (1 << 3) | 154 | #define OMAP24XX_ST_PKA_MASK (1 << 4) |
| 139 | #define OMAP24XX_ST_RNG (1 << 2) | 155 | #define OMAP24XX_ST_AES_SHIFT 3 |
| 140 | #define OMAP24XX_ST_SHA (1 << 1) | 156 | #define OMAP24XX_ST_AES_MASK (1 << 3) |
| 141 | #define OMAP24XX_ST_DES (1 << 0) | 157 | #define OMAP24XX_ST_RNG_SHIFT 2 |
| 158 | #define OMAP24XX_ST_RNG_MASK (1 << 2) | ||
| 159 | #define OMAP24XX_ST_SHA_SHIFT 1 | ||
| 160 | #define OMAP24XX_ST_SHA_MASK (1 << 1) | ||
| 161 | #define OMAP24XX_ST_DES_SHIFT 0 | ||
| 162 | #define OMAP24XX_ST_DES_MASK (1 << 0) | ||
| 142 | 163 | ||
| 143 | /* CM_AUTOIDLE1_CORE */ | 164 | /* CM_AUTOIDLE1_CORE */ |
| 144 | #define OMAP24XX_AUTO_CAM (1 << 31) | 165 | #define OMAP24XX_AUTO_CAM (1 << 31) |
| @@ -275,11 +296,16 @@ | |||
| 275 | #define OMAP24XX_EN_32KSYNC (1 << 1) | 296 | #define OMAP24XX_EN_32KSYNC (1 << 1) |
| 276 | 297 | ||
| 277 | /* CM_IDLEST_WKUP specific bits */ | 298 | /* CM_IDLEST_WKUP specific bits */ |
| 278 | #define OMAP2430_ST_ICR (1 << 6) | 299 | #define OMAP2430_ST_ICR_SHIFT 6 |
| 279 | #define OMAP24XX_ST_OMAPCTRL (1 << 5) | 300 | #define OMAP2430_ST_ICR_MASK (1 << 6) |
| 280 | #define OMAP24XX_ST_WDT1 (1 << 4) | 301 | #define OMAP24XX_ST_OMAPCTRL_SHIFT 5 |
| 281 | #define OMAP24XX_ST_MPU_WDT (1 << 3) | 302 | #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) |
| 282 | #define OMAP24XX_ST_32KSYNC (1 << 1) | 303 | #define OMAP24XX_ST_WDT1_SHIFT 4 |
| 304 | #define OMAP24XX_ST_WDT1_MASK (1 << 4) | ||
| 305 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 | ||
| 306 | #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) | ||
| 307 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 | ||
| 308 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | ||
| 283 | 309 | ||
| 284 | /* CM_AUTOIDLE_WKUP */ | 310 | /* CM_AUTOIDLE_WKUP */ |
| 285 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | 311 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) |