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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-12-16 19:09:12 -0500
committerTony Lindgren <tony@atomide.com>2011-12-16 19:09:12 -0500
commit30c95692f62a40170833e87f3cd50fcbfe87c1a2 (patch)
treee49620b3adc936614c3f5ea3f1466b29952e4fdb /arch/arm/mach-omap2/clock44xx_data.c
parentbfc141e3a515008d85e57af39c9faa4d2bbc65e0 (diff)
ARM: OMAP4: clock: Add CPU local timer clock node
Local timer clock is sourced from the CPU clock and hence changes along with CPU clock. These per CPU local timers are used as clock-events, so they need to be reconfigured on CPU frequency change as part of CPUfreq governor. Newly introduced clockevents_reconfigure() needs to know the twd clock-rate. Provide a clock-node to make clk_get_rate() work for TWD. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: renamed clock node to 'mpu_periphclk' to indicate that this is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved clock and clkdev entries to match the autogenerated script output] Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 0798a802497a..730097ee0f23 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = {
1206 { .parent = NULL }, 1206 { .parent = NULL },
1207}; 1207};
1208 1208
1209static struct clk mpu_periphclk = {
1210 .name = "mpu_periphclk",
1211 .parent = &dpll_mpu_ck,
1212 .ops = &clkops_null,
1213 .fixed_div = 2,
1214 .recalc = &omap_fixed_divisor_recalc,
1215};
1216
1209static struct clk ocp_abe_iclk = { 1217static struct clk ocp_abe_iclk = {
1210 .name = "ocp_abe_iclk", 1218 .name = "ocp_abe_iclk",
1211 .parent = &aess_fclk, 1219 .parent = &aess_fclk,
@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
3189 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 3197 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3190 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 3198 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3191 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 3199 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3200 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
3192 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 3201 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3193 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 3202 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3194 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), 3203 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),