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authorPaul Walmsley <paul@pwsan.com>2009-12-08 18:18:47 -0500
committerpaul <paul@twilight.(none)>2009-12-11 18:12:15 -0500
commit82e9bd588563c4e22ebb55b684ebec7e310cc715 (patch)
treecad50e0c12980a14de3531ec7bf78e3f3e4a3313 /arch/arm/mach-omap2/clock34xx_data.c
parent75d43340113e3822e390f644e8b197737e4c553e (diff)
OMAP3 clock: convert clock34xx.h to clock34xx_data.c
The OMAP3 clock code currently #includes a large .h file full of static data structures. Instead, define the data in a .c file. Russell King <linux@arm.linux.org.uk> proposed this new arrangement: http://marc.info/?l=linux-omap&m=125967425908895&w=2 Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Russell King <linux@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c3289
1 files changed, 3289 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
new file mode 100644
index 000000000000..8bdcc9cc7f9a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -0,0 +1,3289 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/clk.h>
22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
27#include "clock34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30#include "prm.h"
31#include "prm-regbits-34xx.h"
32
33/*
34 * clocks
35 */
36
37#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
38
39/* Maximum DPLL multiplier, divider values for OMAP3 */
40#define OMAP3_MAX_DPLL_MULT 2048
41#define OMAP3_MAX_DPLL_DIV 128
42
43/*
44 * DPLL1 supplies clock to the MPU.
45 * DPLL2 supplies clock to the IVA2.
46 * DPLL3 supplies CORE domain clocks.
47 * DPLL4 supplies peripheral clocks.
48 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
49 */
50
51/* Forward declarations for DPLL bypass clocks */
52static struct clk dpll1_fck;
53static struct clk dpll2_fck;
54
55/* PRM CLOCKS */
56
57/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck",
60 .ops = &clkops_null,
61 .rate = 32768,
62 .flags = RATE_FIXED,
63};
64
65static struct clk secure_32k_fck = {
66 .name = "secure_32k_fck",
67 .ops = &clkops_null,
68 .rate = 32768,
69 .flags = RATE_FIXED,
70};
71
72/* Virtual source clocks for osc_sys_ck */
73static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck",
75 .ops = &clkops_null,
76 .rate = 12000000,
77 .flags = RATE_FIXED,
78};
79
80static struct clk virt_13m_ck = {
81 .name = "virt_13m_ck",
82 .ops = &clkops_null,
83 .rate = 13000000,
84 .flags = RATE_FIXED,
85};
86
87static struct clk virt_16_8m_ck = {
88 .name = "virt_16_8m_ck",
89 .ops = &clkops_null,
90 .rate = 16800000,
91 .flags = RATE_FIXED,
92};
93
94static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
96 .ops = &clkops_null,
97 .rate = 19200000,
98 .flags = RATE_FIXED,
99};
100
101static struct clk virt_26m_ck = {
102 .name = "virt_26m_ck",
103 .ops = &clkops_null,
104 .rate = 26000000,
105 .flags = RATE_FIXED,
106};
107
108static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck",
110 .ops = &clkops_null,
111 .rate = 38400000,
112 .flags = RATE_FIXED,
113};
114
115static const struct clksel_rate osc_sys_12m_rates[] = {
116 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
117 { .div = 0 }
118};
119
120static const struct clksel_rate osc_sys_13m_rates[] = {
121 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
122 { .div = 0 }
123};
124
125static const struct clksel_rate osc_sys_16_8m_rates[] = {
126 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
127 { .div = 0 }
128};
129
130static const struct clksel_rate osc_sys_19_2m_rates[] = {
131 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
132 { .div = 0 }
133};
134
135static const struct clksel_rate osc_sys_26m_rates[] = {
136 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
137 { .div = 0 }
138};
139
140static const struct clksel_rate osc_sys_38_4m_rates[] = {
141 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
142 { .div = 0 }
143};
144
145static const struct clksel osc_sys_clksel[] = {
146 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
147 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
148 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
149 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
150 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
151 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
152 { .parent = NULL },
153};
154
155/* Oscillator clock */
156/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
157static struct clk osc_sys_ck = {
158 .name = "osc_sys_ck",
159 .ops = &clkops_null,
160 .init = &omap2_init_clksel_parent,
161 .clksel_reg = OMAP3430_PRM_CLKSEL,
162 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
163 .clksel = osc_sys_clksel,
164 /* REVISIT: deal with autoextclkmode? */
165 .flags = RATE_FIXED,
166 .recalc = &omap2_clksel_recalc,
167};
168
169static const struct clksel_rate div2_rates[] = {
170 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
171 { .div = 2, .val = 2, .flags = RATE_IN_343X },
172 { .div = 0 }
173};
174
175static const struct clksel sys_clksel[] = {
176 { .parent = &osc_sys_ck, .rates = div2_rates },
177 { .parent = NULL }
178};
179
180/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
181/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
182static struct clk sys_ck = {
183 .name = "sys_ck",
184 .ops = &clkops_null,
185 .parent = &osc_sys_ck,
186 .init = &omap2_init_clksel_parent,
187 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
188 .clksel_mask = OMAP_SYSCLKDIV_MASK,
189 .clksel = sys_clksel,
190 .recalc = &omap2_clksel_recalc,
191};
192
193static struct clk sys_altclk = {
194 .name = "sys_altclk",
195 .ops = &clkops_null,
196};
197
198/* Optional external clock input for some McBSPs */
199static struct clk mcbsp_clks = {
200 .name = "mcbsp_clks",
201 .ops = &clkops_null,
202};
203
204/* PRM EXTERNAL CLOCK OUTPUT */
205
206static struct clk sys_clkout1 = {
207 .name = "sys_clkout1",
208 .ops = &clkops_omap2_dflt,
209 .parent = &osc_sys_ck,
210 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
211 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
212 .recalc = &followparent_recalc,
213};
214
215/* DPLLS */
216
217/* CM CLOCKS */
218
219static const struct clksel_rate div16_dpll_rates[] = {
220 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
221 { .div = 2, .val = 2, .flags = RATE_IN_343X },
222 { .div = 3, .val = 3, .flags = RATE_IN_343X },
223 { .div = 4, .val = 4, .flags = RATE_IN_343X },
224 { .div = 5, .val = 5, .flags = RATE_IN_343X },
225 { .div = 6, .val = 6, .flags = RATE_IN_343X },
226 { .div = 7, .val = 7, .flags = RATE_IN_343X },
227 { .div = 8, .val = 8, .flags = RATE_IN_343X },
228 { .div = 9, .val = 9, .flags = RATE_IN_343X },
229 { .div = 10, .val = 10, .flags = RATE_IN_343X },
230 { .div = 11, .val = 11, .flags = RATE_IN_343X },
231 { .div = 12, .val = 12, .flags = RATE_IN_343X },
232 { .div = 13, .val = 13, .flags = RATE_IN_343X },
233 { .div = 14, .val = 14, .flags = RATE_IN_343X },
234 { .div = 15, .val = 15, .flags = RATE_IN_343X },
235 { .div = 16, .val = 16, .flags = RATE_IN_343X },
236 { .div = 0 }
237};
238
239/* DPLL1 */
240/* MPU clock source */
241/* Type: DPLL */
242static struct dpll_data dpll1_dd = {
243 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
244 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
245 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
246 .clk_bypass = &dpll1_fck,
247 .clk_ref = &sys_ck,
248 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
249 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
250 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
251 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
252 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
253 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
254 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
255 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
256 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
257 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
258 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
259 .max_multiplier = OMAP3_MAX_DPLL_MULT,
260 .min_divider = 1,
261 .max_divider = OMAP3_MAX_DPLL_DIV,
262 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
263};
264
265static struct clk dpll1_ck = {
266 .name = "dpll1_ck",
267 .ops = &clkops_null,
268 .parent = &sys_ck,
269 .dpll_data = &dpll1_dd,
270 .round_rate = &omap2_dpll_round_rate,
271 .set_rate = &omap3_noncore_dpll_set_rate,
272 .clkdm_name = "dpll1_clkdm",
273 .recalc = &omap3_dpll_recalc,
274};
275
276/*
277 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
278 * DPLL isn't bypassed.
279 */
280static struct clk dpll1_x2_ck = {
281 .name = "dpll1_x2_ck",
282 .ops = &clkops_null,
283 .parent = &dpll1_ck,
284 .clkdm_name = "dpll1_clkdm",
285 .recalc = &omap3_clkoutx2_recalc,
286};
287
288/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
289static const struct clksel div16_dpll1_x2m2_clksel[] = {
290 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
291 { .parent = NULL }
292};
293
294/*
295 * Does not exist in the TRM - needed to separate the M2 divider from
296 * bypass selection in mpu_ck
297 */
298static struct clk dpll1_x2m2_ck = {
299 .name = "dpll1_x2m2_ck",
300 .ops = &clkops_null,
301 .parent = &dpll1_x2_ck,
302 .init = &omap2_init_clksel_parent,
303 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
304 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
305 .clksel = div16_dpll1_x2m2_clksel,
306 .clkdm_name = "dpll1_clkdm",
307 .recalc = &omap2_clksel_recalc,
308};
309
310/* DPLL2 */
311/* IVA2 clock source */
312/* Type: DPLL */
313
314static struct dpll_data dpll2_dd = {
315 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
316 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
317 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
318 .clk_bypass = &dpll2_fck,
319 .clk_ref = &sys_ck,
320 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
321 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
322 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
323 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
324 (1 << DPLL_LOW_POWER_BYPASS),
325 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
326 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
327 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
328 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
329 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
330 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
331 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
332 .max_multiplier = OMAP3_MAX_DPLL_MULT,
333 .min_divider = 1,
334 .max_divider = OMAP3_MAX_DPLL_DIV,
335 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
336};
337
338static struct clk dpll2_ck = {
339 .name = "dpll2_ck",
340 .ops = &clkops_noncore_dpll_ops,
341 .parent = &sys_ck,
342 .dpll_data = &dpll2_dd,
343 .round_rate = &omap2_dpll_round_rate,
344 .set_rate = &omap3_noncore_dpll_set_rate,
345 .clkdm_name = "dpll2_clkdm",
346 .recalc = &omap3_dpll_recalc,
347};
348
349static const struct clksel div16_dpll2_m2x2_clksel[] = {
350 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
351 { .parent = NULL }
352};
353
354/*
355 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
356 * or CLKOUTX2. CLKOUT seems most plausible.
357 */
358static struct clk dpll2_m2_ck = {
359 .name = "dpll2_m2_ck",
360 .ops = &clkops_null,
361 .parent = &dpll2_ck,
362 .init = &omap2_init_clksel_parent,
363 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
364 OMAP3430_CM_CLKSEL2_PLL),
365 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
366 .clksel = div16_dpll2_m2x2_clksel,
367 .clkdm_name = "dpll2_clkdm",
368 .recalc = &omap2_clksel_recalc,
369};
370
371/*
372 * DPLL3
373 * Source clock for all interfaces and for some device fclks
374 * REVISIT: Also supports fast relock bypass - not included below
375 */
376static struct dpll_data dpll3_dd = {
377 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
378 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
379 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
380 .clk_bypass = &sys_ck,
381 .clk_ref = &sys_ck,
382 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
383 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
384 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
385 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
386 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
387 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
388 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
389 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
390 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
391 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
392 .max_multiplier = OMAP3_MAX_DPLL_MULT,
393 .min_divider = 1,
394 .max_divider = OMAP3_MAX_DPLL_DIV,
395 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
396};
397
398static struct clk dpll3_ck = {
399 .name = "dpll3_ck",
400 .ops = &clkops_null,
401 .parent = &sys_ck,
402 .dpll_data = &dpll3_dd,
403 .round_rate = &omap2_dpll_round_rate,
404 .clkdm_name = "dpll3_clkdm",
405 .recalc = &omap3_dpll_recalc,
406};
407
408/*
409 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
410 * DPLL isn't bypassed
411 */
412static struct clk dpll3_x2_ck = {
413 .name = "dpll3_x2_ck",
414 .ops = &clkops_null,
415 .parent = &dpll3_ck,
416 .clkdm_name = "dpll3_clkdm",
417 .recalc = &omap3_clkoutx2_recalc,
418};
419
420static const struct clksel_rate div31_dpll3_rates[] = {
421 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
422 { .div = 2, .val = 2, .flags = RATE_IN_343X },
423 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
424 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
425 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
426 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
427 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
428 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
429 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
430 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
431 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
432 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
433 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
434 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
435 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
436 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
437 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
438 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
439 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
440 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
441 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
442 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
443 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
444 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
445 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
446 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
447 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
448 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
449 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
450 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
451 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
452 { .div = 0 },
453};
454
455static const struct clksel div31_dpll3m2_clksel[] = {
456 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
457 { .parent = NULL }
458};
459
460/* DPLL3 output M2 - primary control point for CORE speed */
461static struct clk dpll3_m2_ck = {
462 .name = "dpll3_m2_ck",
463 .ops = &clkops_null,
464 .parent = &dpll3_ck,
465 .init = &omap2_init_clksel_parent,
466 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
467 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
468 .clksel = div31_dpll3m2_clksel,
469 .clkdm_name = "dpll3_clkdm",
470 .round_rate = &omap2_clksel_round_rate,
471 .set_rate = &omap3_core_dpll_m2_set_rate,
472 .recalc = &omap2_clksel_recalc,
473};
474
475static struct clk core_ck = {
476 .name = "core_ck",
477 .ops = &clkops_null,
478 .parent = &dpll3_m2_ck,
479 .recalc = &followparent_recalc,
480};
481
482static struct clk dpll3_m2x2_ck = {
483 .name = "dpll3_m2x2_ck",
484 .ops = &clkops_null,
485 .parent = &dpll3_m2_ck,
486 .clkdm_name = "dpll3_clkdm",
487 .recalc = &omap3_clkoutx2_recalc,
488};
489
490/* The PWRDN bit is apparently only available on 3430ES2 and above */
491static const struct clksel div16_dpll3_clksel[] = {
492 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
493 { .parent = NULL }
494};
495
496/* This virtual clock is the source for dpll3_m3x2_ck */
497static struct clk dpll3_m3_ck = {
498 .name = "dpll3_m3_ck",
499 .ops = &clkops_null,
500 .parent = &dpll3_ck,
501 .init = &omap2_init_clksel_parent,
502 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
503 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
504 .clksel = div16_dpll3_clksel,
505 .clkdm_name = "dpll3_clkdm",
506 .recalc = &omap2_clksel_recalc,
507};
508
509/* The PWRDN bit is apparently only available on 3430ES2 and above */
510static struct clk dpll3_m3x2_ck = {
511 .name = "dpll3_m3x2_ck",
512 .ops = &clkops_omap2_dflt_wait,
513 .parent = &dpll3_m3_ck,
514 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
515 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
516 .flags = INVERT_ENABLE,
517 .clkdm_name = "dpll3_clkdm",
518 .recalc = &omap3_clkoutx2_recalc,
519};
520
521static struct clk emu_core_alwon_ck = {
522 .name = "emu_core_alwon_ck",
523 .ops = &clkops_null,
524 .parent = &dpll3_m3x2_ck,
525 .clkdm_name = "dpll3_clkdm",
526 .recalc = &followparent_recalc,
527};
528
529/* DPLL4 */
530/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
531/* Type: DPLL */
532static struct dpll_data dpll4_dd = {
533 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
534 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
535 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
536 .clk_bypass = &sys_ck,
537 .clk_ref = &sys_ck,
538 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
539 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
540 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
541 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
542 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
543 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
544 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
545 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
546 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
547 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
548 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
549 .max_multiplier = OMAP3_MAX_DPLL_MULT,
550 .min_divider = 1,
551 .max_divider = OMAP3_MAX_DPLL_DIV,
552 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
553};
554
555static struct clk dpll4_ck = {
556 .name = "dpll4_ck",
557 .ops = &clkops_noncore_dpll_ops,
558 .parent = &sys_ck,
559 .dpll_data = &dpll4_dd,
560 .round_rate = &omap2_dpll_round_rate,
561 .set_rate = &omap3_dpll4_set_rate,
562 .clkdm_name = "dpll4_clkdm",
563 .recalc = &omap3_dpll_recalc,
564};
565
566/*
567 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
568 * DPLL isn't bypassed --
569 * XXX does this serve any downstream clocks?
570 */
571static struct clk dpll4_x2_ck = {
572 .name = "dpll4_x2_ck",
573 .ops = &clkops_null,
574 .parent = &dpll4_ck,
575 .clkdm_name = "dpll4_clkdm",
576 .recalc = &omap3_clkoutx2_recalc,
577};
578
579static const struct clksel div16_dpll4_clksel[] = {
580 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
581 { .parent = NULL }
582};
583
584/* This virtual clock is the source for dpll4_m2x2_ck */
585static struct clk dpll4_m2_ck = {
586 .name = "dpll4_m2_ck",
587 .ops = &clkops_null,
588 .parent = &dpll4_ck,
589 .init = &omap2_init_clksel_parent,
590 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
591 .clksel_mask = OMAP3430_DIV_96M_MASK,
592 .clksel = div16_dpll4_clksel,
593 .clkdm_name = "dpll4_clkdm",
594 .recalc = &omap2_clksel_recalc,
595};
596
597/* The PWRDN bit is apparently only available on 3430ES2 and above */
598static struct clk dpll4_m2x2_ck = {
599 .name = "dpll4_m2x2_ck",
600 .ops = &clkops_omap2_dflt_wait,
601 .parent = &dpll4_m2_ck,
602 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
603 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
604 .flags = INVERT_ENABLE,
605 .clkdm_name = "dpll4_clkdm",
606 .recalc = &omap3_clkoutx2_recalc,
607};
608
609/*
610 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
611 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
612 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
613 * CM_96K_(F)CLK.
614 */
615static struct clk omap_96m_alwon_fck = {
616 .name = "omap_96m_alwon_fck",
617 .ops = &clkops_null,
618 .parent = &dpll4_m2x2_ck,
619 .recalc = &followparent_recalc,
620};
621
622static struct clk cm_96m_fck = {
623 .name = "cm_96m_fck",
624 .ops = &clkops_null,
625 .parent = &omap_96m_alwon_fck,
626 .recalc = &followparent_recalc,
627};
628
629static const struct clksel_rate omap_96m_dpll_rates[] = {
630 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
631 { .div = 0 }
632};
633
634static const struct clksel_rate omap_96m_sys_rates[] = {
635 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
636 { .div = 0 }
637};
638
639static const struct clksel omap_96m_fck_clksel[] = {
640 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
641 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
642 { .parent = NULL }
643};
644
645static struct clk omap_96m_fck = {
646 .name = "omap_96m_fck",
647 .ops = &clkops_null,
648 .parent = &sys_ck,
649 .init = &omap2_init_clksel_parent,
650 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
651 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
652 .clksel = omap_96m_fck_clksel,
653 .recalc = &omap2_clksel_recalc,
654};
655
656/* This virtual clock is the source for dpll4_m3x2_ck */
657static struct clk dpll4_m3_ck = {
658 .name = "dpll4_m3_ck",
659 .ops = &clkops_null,
660 .parent = &dpll4_ck,
661 .init = &omap2_init_clksel_parent,
662 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
663 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
664 .clksel = div16_dpll4_clksel,
665 .clkdm_name = "dpll4_clkdm",
666 .recalc = &omap2_clksel_recalc,
667};
668
669/* The PWRDN bit is apparently only available on 3430ES2 and above */
670static struct clk dpll4_m3x2_ck = {
671 .name = "dpll4_m3x2_ck",
672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &dpll4_m3_ck,
674 .init = &omap2_init_clksel_parent,
675 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
676 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
677 .flags = INVERT_ENABLE,
678 .clkdm_name = "dpll4_clkdm",
679 .recalc = &omap3_clkoutx2_recalc,
680};
681
682static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
683 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
684 { .div = 0 }
685};
686
687static const struct clksel_rate omap_54m_alt_rates[] = {
688 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
689 { .div = 0 }
690};
691
692static const struct clksel omap_54m_clksel[] = {
693 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
694 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
695 { .parent = NULL }
696};
697
698static struct clk omap_54m_fck = {
699 .name = "omap_54m_fck",
700 .ops = &clkops_null,
701 .init = &omap2_init_clksel_parent,
702 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
703 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
704 .clksel = omap_54m_clksel,
705 .recalc = &omap2_clksel_recalc,
706};
707
708static const struct clksel_rate omap_48m_cm96m_rates[] = {
709 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
710 { .div = 0 }
711};
712
713static const struct clksel_rate omap_48m_alt_rates[] = {
714 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
715 { .div = 0 }
716};
717
718static const struct clksel omap_48m_clksel[] = {
719 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
720 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
721 { .parent = NULL }
722};
723
724static struct clk omap_48m_fck = {
725 .name = "omap_48m_fck",
726 .ops = &clkops_null,
727 .init = &omap2_init_clksel_parent,
728 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
729 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
730 .clksel = omap_48m_clksel,
731 .recalc = &omap2_clksel_recalc,
732};
733
734static struct clk omap_12m_fck = {
735 .name = "omap_12m_fck",
736 .ops = &clkops_null,
737 .parent = &omap_48m_fck,
738 .fixed_div = 4,
739 .recalc = &omap2_fixed_divisor_recalc,
740};
741
742/* This virstual clock is the source for dpll4_m4x2_ck */
743static struct clk dpll4_m4_ck = {
744 .name = "dpll4_m4_ck",
745 .ops = &clkops_null,
746 .parent = &dpll4_ck,
747 .init = &omap2_init_clksel_parent,
748 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
749 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
750 .clksel = div16_dpll4_clksel,
751 .clkdm_name = "dpll4_clkdm",
752 .recalc = &omap2_clksel_recalc,
753 .set_rate = &omap2_clksel_set_rate,
754 .round_rate = &omap2_clksel_round_rate,
755};
756
757/* The PWRDN bit is apparently only available on 3430ES2 and above */
758static struct clk dpll4_m4x2_ck = {
759 .name = "dpll4_m4x2_ck",
760 .ops = &clkops_omap2_dflt_wait,
761 .parent = &dpll4_m4_ck,
762 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
763 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
764 .flags = INVERT_ENABLE,
765 .clkdm_name = "dpll4_clkdm",
766 .recalc = &omap3_clkoutx2_recalc,
767};
768
769/* This virtual clock is the source for dpll4_m5x2_ck */
770static struct clk dpll4_m5_ck = {
771 .name = "dpll4_m5_ck",
772 .ops = &clkops_null,
773 .parent = &dpll4_ck,
774 .init = &omap2_init_clksel_parent,
775 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
776 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
777 .clksel = div16_dpll4_clksel,
778 .clkdm_name = "dpll4_clkdm",
779 .recalc = &omap2_clksel_recalc,
780};
781
782/* The PWRDN bit is apparently only available on 3430ES2 and above */
783static struct clk dpll4_m5x2_ck = {
784 .name = "dpll4_m5x2_ck",
785 .ops = &clkops_omap2_dflt_wait,
786 .parent = &dpll4_m5_ck,
787 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
788 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
789 .flags = INVERT_ENABLE,
790 .clkdm_name = "dpll4_clkdm",
791 .recalc = &omap3_clkoutx2_recalc,
792};
793
794/* This virtual clock is the source for dpll4_m6x2_ck */
795static struct clk dpll4_m6_ck = {
796 .name = "dpll4_m6_ck",
797 .ops = &clkops_null,
798 .parent = &dpll4_ck,
799 .init = &omap2_init_clksel_parent,
800 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
801 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
802 .clksel = div16_dpll4_clksel,
803 .clkdm_name = "dpll4_clkdm",
804 .recalc = &omap2_clksel_recalc,
805};
806
807/* The PWRDN bit is apparently only available on 3430ES2 and above */
808static struct clk dpll4_m6x2_ck = {
809 .name = "dpll4_m6x2_ck",
810 .ops = &clkops_omap2_dflt_wait,
811 .parent = &dpll4_m6_ck,
812 .init = &omap2_init_clksel_parent,
813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
814 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
815 .flags = INVERT_ENABLE,
816 .clkdm_name = "dpll4_clkdm",
817 .recalc = &omap3_clkoutx2_recalc,
818};
819
820static struct clk emu_per_alwon_ck = {
821 .name = "emu_per_alwon_ck",
822 .ops = &clkops_null,
823 .parent = &dpll4_m6x2_ck,
824 .clkdm_name = "dpll4_clkdm",
825 .recalc = &followparent_recalc,
826};
827
828/* DPLL5 */
829/* Supplies 120MHz clock, USIM source clock */
830/* Type: DPLL */
831/* 3430ES2 only */
832static struct dpll_data dpll5_dd = {
833 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
834 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
835 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
836 .clk_bypass = &sys_ck,
837 .clk_ref = &sys_ck,
838 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
839 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
840 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
841 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
842 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
843 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
844 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
845 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
846 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
847 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
848 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
849 .max_multiplier = OMAP3_MAX_DPLL_MULT,
850 .min_divider = 1,
851 .max_divider = OMAP3_MAX_DPLL_DIV,
852 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
853};
854
855static struct clk dpll5_ck = {
856 .name = "dpll5_ck",
857 .ops = &clkops_noncore_dpll_ops,
858 .parent = &sys_ck,
859 .dpll_data = &dpll5_dd,
860 .round_rate = &omap2_dpll_round_rate,
861 .set_rate = &omap3_noncore_dpll_set_rate,
862 .clkdm_name = "dpll5_clkdm",
863 .recalc = &omap3_dpll_recalc,
864};
865
866static const struct clksel div16_dpll5_clksel[] = {
867 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
868 { .parent = NULL }
869};
870
871static struct clk dpll5_m2_ck = {
872 .name = "dpll5_m2_ck",
873 .ops = &clkops_null,
874 .parent = &dpll5_ck,
875 .init = &omap2_init_clksel_parent,
876 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
877 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
878 .clksel = div16_dpll5_clksel,
879 .clkdm_name = "dpll5_clkdm",
880 .recalc = &omap2_clksel_recalc,
881};
882
883/* CM EXTERNAL CLOCK OUTPUTS */
884
885static const struct clksel_rate clkout2_src_core_rates[] = {
886 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
887 { .div = 0 }
888};
889
890static const struct clksel_rate clkout2_src_sys_rates[] = {
891 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
892 { .div = 0 }
893};
894
895static const struct clksel_rate clkout2_src_96m_rates[] = {
896 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
897 { .div = 0 }
898};
899
900static const struct clksel_rate clkout2_src_54m_rates[] = {
901 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
902 { .div = 0 }
903};
904
905static const struct clksel clkout2_src_clksel[] = {
906 { .parent = &core_ck, .rates = clkout2_src_core_rates },
907 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
908 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
909 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
910 { .parent = NULL }
911};
912
913static struct clk clkout2_src_ck = {
914 .name = "clkout2_src_ck",
915 .ops = &clkops_omap2_dflt,
916 .init = &omap2_init_clksel_parent,
917 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
918 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
919 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
920 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
921 .clksel = clkout2_src_clksel,
922 .clkdm_name = "core_clkdm",
923 .recalc = &omap2_clksel_recalc,
924};
925
926static const struct clksel_rate sys_clkout2_rates[] = {
927 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
928 { .div = 2, .val = 1, .flags = RATE_IN_343X },
929 { .div = 4, .val = 2, .flags = RATE_IN_343X },
930 { .div = 8, .val = 3, .flags = RATE_IN_343X },
931 { .div = 16, .val = 4, .flags = RATE_IN_343X },
932 { .div = 0 },
933};
934
935static const struct clksel sys_clkout2_clksel[] = {
936 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
937 { .parent = NULL },
938};
939
940static struct clk sys_clkout2 = {
941 .name = "sys_clkout2",
942 .ops = &clkops_null,
943 .init = &omap2_init_clksel_parent,
944 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
945 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
946 .clksel = sys_clkout2_clksel,
947 .recalc = &omap2_clksel_recalc,
948};
949
950/* CM OUTPUT CLOCKS */
951
952static struct clk corex2_fck = {
953 .name = "corex2_fck",
954 .ops = &clkops_null,
955 .parent = &dpll3_m2x2_ck,
956 .recalc = &followparent_recalc,
957};
958
959/* DPLL power domain clock controls */
960
961static const struct clksel_rate div4_rates[] = {
962 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
963 { .div = 2, .val = 2, .flags = RATE_IN_343X },
964 { .div = 4, .val = 4, .flags = RATE_IN_343X },
965 { .div = 0 }
966};
967
968static const struct clksel div4_core_clksel[] = {
969 { .parent = &core_ck, .rates = div4_rates },
970 { .parent = NULL }
971};
972
973/*
974 * REVISIT: Are these in DPLL power domain or CM power domain? docs
975 * may be inconsistent here?
976 */
977static struct clk dpll1_fck = {
978 .name = "dpll1_fck",
979 .ops = &clkops_null,
980 .parent = &core_ck,
981 .init = &omap2_init_clksel_parent,
982 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
983 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
984 .clksel = div4_core_clksel,
985 .recalc = &omap2_clksel_recalc,
986};
987
988static struct clk mpu_ck = {
989 .name = "mpu_ck",
990 .ops = &clkops_null,
991 .parent = &dpll1_x2m2_ck,
992 .clkdm_name = "mpu_clkdm",
993 .recalc = &followparent_recalc,
994};
995
996/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
997static const struct clksel_rate arm_fck_rates[] = {
998 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
999 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1000 { .div = 0 },
1001};
1002
1003static const struct clksel arm_fck_clksel[] = {
1004 { .parent = &mpu_ck, .rates = arm_fck_rates },
1005 { .parent = NULL }
1006};
1007
1008static struct clk arm_fck = {
1009 .name = "arm_fck",
1010 .ops = &clkops_null,
1011 .parent = &mpu_ck,
1012 .init = &omap2_init_clksel_parent,
1013 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1014 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1015 .clksel = arm_fck_clksel,
1016 .clkdm_name = "mpu_clkdm",
1017 .recalc = &omap2_clksel_recalc,
1018};
1019
1020/* XXX What about neon_clkdm ? */
1021
1022/*
1023 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1024 * although it is referenced - so this is a guess
1025 */
1026static struct clk emu_mpu_alwon_ck = {
1027 .name = "emu_mpu_alwon_ck",
1028 .ops = &clkops_null,
1029 .parent = &mpu_ck,
1030 .recalc = &followparent_recalc,
1031};
1032
1033static struct clk dpll2_fck = {
1034 .name = "dpll2_fck",
1035 .ops = &clkops_null,
1036 .parent = &core_ck,
1037 .init = &omap2_init_clksel_parent,
1038 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1039 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1040 .clksel = div4_core_clksel,
1041 .recalc = &omap2_clksel_recalc,
1042};
1043
1044static struct clk iva2_ck = {
1045 .name = "iva2_ck",
1046 .ops = &clkops_omap2_dflt_wait,
1047 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent,
1049 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1050 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1051 .clkdm_name = "iva2_clkdm",
1052 .recalc = &followparent_recalc,
1053};
1054
1055/* Common interface clocks */
1056
1057static const struct clksel div2_core_clksel[] = {
1058 { .parent = &core_ck, .rates = div2_rates },
1059 { .parent = NULL }
1060};
1061
1062static struct clk l3_ick = {
1063 .name = "l3_ick",
1064 .ops = &clkops_null,
1065 .parent = &core_ck,
1066 .init = &omap2_init_clksel_parent,
1067 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1068 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1069 .clksel = div2_core_clksel,
1070 .clkdm_name = "core_l3_clkdm",
1071 .recalc = &omap2_clksel_recalc,
1072};
1073
1074static const struct clksel div2_l3_clksel[] = {
1075 { .parent = &l3_ick, .rates = div2_rates },
1076 { .parent = NULL }
1077};
1078
1079static struct clk l4_ick = {
1080 .name = "l4_ick",
1081 .ops = &clkops_null,
1082 .parent = &l3_ick,
1083 .init = &omap2_init_clksel_parent,
1084 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1085 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1086 .clksel = div2_l3_clksel,
1087 .clkdm_name = "core_l4_clkdm",
1088 .recalc = &omap2_clksel_recalc,
1089
1090};
1091
1092static const struct clksel div2_l4_clksel[] = {
1093 { .parent = &l4_ick, .rates = div2_rates },
1094 { .parent = NULL }
1095};
1096
1097static struct clk rm_ick = {
1098 .name = "rm_ick",
1099 .ops = &clkops_null,
1100 .parent = &l4_ick,
1101 .init = &omap2_init_clksel_parent,
1102 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1103 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1104 .clksel = div2_l4_clksel,
1105 .recalc = &omap2_clksel_recalc,
1106};
1107
1108/* GFX power domain */
1109
1110/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1111
1112static const struct clksel gfx_l3_clksel[] = {
1113 { .parent = &l3_ick, .rates = gfx_l3_rates },
1114 { .parent = NULL }
1115};
1116
1117/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1118static struct clk gfx_l3_ck = {
1119 .name = "gfx_l3_ck",
1120 .ops = &clkops_omap2_dflt_wait,
1121 .parent = &l3_ick,
1122 .init = &omap2_init_clksel_parent,
1123 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1124 .enable_bit = OMAP_EN_GFX_SHIFT,
1125 .recalc = &followparent_recalc,
1126};
1127
1128static struct clk gfx_l3_fck = {
1129 .name = "gfx_l3_fck",
1130 .ops = &clkops_null,
1131 .parent = &gfx_l3_ck,
1132 .init = &omap2_init_clksel_parent,
1133 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1134 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1135 .clksel = gfx_l3_clksel,
1136 .clkdm_name = "gfx_3430es1_clkdm",
1137 .recalc = &omap2_clksel_recalc,
1138};
1139
1140static struct clk gfx_l3_ick = {
1141 .name = "gfx_l3_ick",
1142 .ops = &clkops_null,
1143 .parent = &gfx_l3_ck,
1144 .clkdm_name = "gfx_3430es1_clkdm",
1145 .recalc = &followparent_recalc,
1146};
1147
1148static struct clk gfx_cg1_ck = {
1149 .name = "gfx_cg1_ck",
1150 .ops = &clkops_omap2_dflt_wait,
1151 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1152 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1153 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1154 .clkdm_name = "gfx_3430es1_clkdm",
1155 .recalc = &followparent_recalc,
1156};
1157
1158static struct clk gfx_cg2_ck = {
1159 .name = "gfx_cg2_ck",
1160 .ops = &clkops_omap2_dflt_wait,
1161 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1162 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1163 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1164 .clkdm_name = "gfx_3430es1_clkdm",
1165 .recalc = &followparent_recalc,
1166};
1167
1168/* SGX power domain - 3430ES2 only */
1169
1170static const struct clksel_rate sgx_core_rates[] = {
1171 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1172 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1173 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1174 { .div = 0 },
1175};
1176
1177static const struct clksel_rate sgx_96m_rates[] = {
1178 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1179 { .div = 0 },
1180};
1181
1182static const struct clksel sgx_clksel[] = {
1183 { .parent = &core_ck, .rates = sgx_core_rates },
1184 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1185 { .parent = NULL },
1186};
1187
1188static struct clk sgx_fck = {
1189 .name = "sgx_fck",
1190 .ops = &clkops_omap2_dflt_wait,
1191 .init = &omap2_init_clksel_parent,
1192 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1193 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1194 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1195 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1196 .clksel = sgx_clksel,
1197 .clkdm_name = "sgx_clkdm",
1198 .recalc = &omap2_clksel_recalc,
1199};
1200
1201static struct clk sgx_ick = {
1202 .name = "sgx_ick",
1203 .ops = &clkops_omap2_dflt_wait,
1204 .parent = &l3_ick,
1205 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1206 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1207 .clkdm_name = "sgx_clkdm",
1208 .recalc = &followparent_recalc,
1209};
1210
1211/* CORE power domain */
1212
1213static struct clk d2d_26m_fck = {
1214 .name = "d2d_26m_fck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &sys_ck,
1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1218 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1219 .clkdm_name = "d2d_clkdm",
1220 .recalc = &followparent_recalc,
1221};
1222
1223static struct clk modem_fck = {
1224 .name = "modem_fck",
1225 .ops = &clkops_omap2_dflt_wait,
1226 .parent = &sys_ck,
1227 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1228 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1229 .clkdm_name = "d2d_clkdm",
1230 .recalc = &followparent_recalc,
1231};
1232
1233static struct clk sad2d_ick = {
1234 .name = "sad2d_ick",
1235 .ops = &clkops_omap2_dflt_wait,
1236 .parent = &l3_ick,
1237 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1238 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1239 .clkdm_name = "d2d_clkdm",
1240 .recalc = &followparent_recalc,
1241};
1242
1243static struct clk mad2d_ick = {
1244 .name = "mad2d_ick",
1245 .ops = &clkops_omap2_dflt_wait,
1246 .parent = &l3_ick,
1247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1248 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1249 .clkdm_name = "d2d_clkdm",
1250 .recalc = &followparent_recalc,
1251};
1252
1253static const struct clksel omap343x_gpt_clksel[] = {
1254 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1255 { .parent = &sys_ck, .rates = gpt_sys_rates },
1256 { .parent = NULL}
1257};
1258
1259static struct clk gpt10_fck = {
1260 .name = "gpt10_fck",
1261 .ops = &clkops_omap2_dflt_wait,
1262 .parent = &sys_ck,
1263 .init = &omap2_init_clksel_parent,
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1265 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1268 .clksel = omap343x_gpt_clksel,
1269 .clkdm_name = "core_l4_clkdm",
1270 .recalc = &omap2_clksel_recalc,
1271};
1272
1273static struct clk gpt11_fck = {
1274 .name = "gpt11_fck",
1275 .ops = &clkops_omap2_dflt_wait,
1276 .parent = &sys_ck,
1277 .init = &omap2_init_clksel_parent,
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1279 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1280 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1281 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1282 .clksel = omap343x_gpt_clksel,
1283 .clkdm_name = "core_l4_clkdm",
1284 .recalc = &omap2_clksel_recalc,
1285};
1286
1287static struct clk cpefuse_fck = {
1288 .name = "cpefuse_fck",
1289 .ops = &clkops_omap2_dflt,
1290 .parent = &sys_ck,
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1292 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1293 .recalc = &followparent_recalc,
1294};
1295
1296static struct clk ts_fck = {
1297 .name = "ts_fck",
1298 .ops = &clkops_omap2_dflt,
1299 .parent = &omap_32k_fck,
1300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1301 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1302 .recalc = &followparent_recalc,
1303};
1304
1305static struct clk usbtll_fck = {
1306 .name = "usbtll_fck",
1307 .ops = &clkops_omap2_dflt,
1308 .parent = &dpll5_m2_ck,
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1310 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1311 .recalc = &followparent_recalc,
1312};
1313
1314/* CORE 96M FCLK-derived clocks */
1315
1316static struct clk core_96m_fck = {
1317 .name = "core_96m_fck",
1318 .ops = &clkops_null,
1319 .parent = &omap_96m_fck,
1320 .clkdm_name = "core_l4_clkdm",
1321 .recalc = &followparent_recalc,
1322};
1323
1324static struct clk mmchs3_fck = {
1325 .name = "mmchs_fck",
1326 .ops = &clkops_omap2_dflt_wait,
1327 .id = 2,
1328 .parent = &core_96m_fck,
1329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1330 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1331 .clkdm_name = "core_l4_clkdm",
1332 .recalc = &followparent_recalc,
1333};
1334
1335static struct clk mmchs2_fck = {
1336 .name = "mmchs_fck",
1337 .ops = &clkops_omap2_dflt_wait,
1338 .id = 1,
1339 .parent = &core_96m_fck,
1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1342 .clkdm_name = "core_l4_clkdm",
1343 .recalc = &followparent_recalc,
1344};
1345
1346static struct clk mspro_fck = {
1347 .name = "mspro_fck",
1348 .ops = &clkops_omap2_dflt_wait,
1349 .parent = &core_96m_fck,
1350 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1351 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1352 .clkdm_name = "core_l4_clkdm",
1353 .recalc = &followparent_recalc,
1354};
1355
1356static struct clk mmchs1_fck = {
1357 .name = "mmchs_fck",
1358 .ops = &clkops_omap2_dflt_wait,
1359 .parent = &core_96m_fck,
1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1361 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1362 .clkdm_name = "core_l4_clkdm",
1363 .recalc = &followparent_recalc,
1364};
1365
1366static struct clk i2c3_fck = {
1367 .name = "i2c_fck",
1368 .ops = &clkops_omap2_dflt_wait,
1369 .id = 3,
1370 .parent = &core_96m_fck,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1373 .clkdm_name = "core_l4_clkdm",
1374 .recalc = &followparent_recalc,
1375};
1376
1377static struct clk i2c2_fck = {
1378 .name = "i2c_fck",
1379 .ops = &clkops_omap2_dflt_wait,
1380 .id = 2,
1381 .parent = &core_96m_fck,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1384 .clkdm_name = "core_l4_clkdm",
1385 .recalc = &followparent_recalc,
1386};
1387
1388static struct clk i2c1_fck = {
1389 .name = "i2c_fck",
1390 .ops = &clkops_omap2_dflt_wait,
1391 .id = 1,
1392 .parent = &core_96m_fck,
1393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1394 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1395 .clkdm_name = "core_l4_clkdm",
1396 .recalc = &followparent_recalc,
1397};
1398
1399/*
1400 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1401 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1402 */
1403static const struct clksel_rate common_mcbsp_96m_rates[] = {
1404 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1405 { .div = 0 }
1406};
1407
1408static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1409 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1410 { .div = 0 }
1411};
1412
1413static const struct clksel mcbsp_15_clksel[] = {
1414 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1415 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1416 { .parent = NULL }
1417};
1418
1419static struct clk mcbsp5_fck = {
1420 .name = "mcbsp_fck",
1421 .ops = &clkops_omap2_dflt_wait,
1422 .id = 5,
1423 .init = &omap2_init_clksel_parent,
1424 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1425 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1426 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1427 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1428 .clksel = mcbsp_15_clksel,
1429 .clkdm_name = "core_l4_clkdm",
1430 .recalc = &omap2_clksel_recalc,
1431};
1432
1433static struct clk mcbsp1_fck = {
1434 .name = "mcbsp_fck",
1435 .ops = &clkops_omap2_dflt_wait,
1436 .id = 1,
1437 .init = &omap2_init_clksel_parent,
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1440 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1441 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1442 .clksel = mcbsp_15_clksel,
1443 .clkdm_name = "core_l4_clkdm",
1444 .recalc = &omap2_clksel_recalc,
1445};
1446
1447/* CORE_48M_FCK-derived clocks */
1448
1449static struct clk core_48m_fck = {
1450 .name = "core_48m_fck",
1451 .ops = &clkops_null,
1452 .parent = &omap_48m_fck,
1453 .clkdm_name = "core_l4_clkdm",
1454 .recalc = &followparent_recalc,
1455};
1456
1457static struct clk mcspi4_fck = {
1458 .name = "mcspi_fck",
1459 .ops = &clkops_omap2_dflt_wait,
1460 .id = 4,
1461 .parent = &core_48m_fck,
1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1464 .recalc = &followparent_recalc,
1465};
1466
1467static struct clk mcspi3_fck = {
1468 .name = "mcspi_fck",
1469 .ops = &clkops_omap2_dflt_wait,
1470 .id = 3,
1471 .parent = &core_48m_fck,
1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1474 .recalc = &followparent_recalc,
1475};
1476
1477static struct clk mcspi2_fck = {
1478 .name = "mcspi_fck",
1479 .ops = &clkops_omap2_dflt_wait,
1480 .id = 2,
1481 .parent = &core_48m_fck,
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1484 .recalc = &followparent_recalc,
1485};
1486
1487static struct clk mcspi1_fck = {
1488 .name = "mcspi_fck",
1489 .ops = &clkops_omap2_dflt_wait,
1490 .id = 1,
1491 .parent = &core_48m_fck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1494 .recalc = &followparent_recalc,
1495};
1496
1497static struct clk uart2_fck = {
1498 .name = "uart2_fck",
1499 .ops = &clkops_omap2_dflt_wait,
1500 .parent = &core_48m_fck,
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1502 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1503 .recalc = &followparent_recalc,
1504};
1505
1506static struct clk uart1_fck = {
1507 .name = "uart1_fck",
1508 .ops = &clkops_omap2_dflt_wait,
1509 .parent = &core_48m_fck,
1510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1512 .recalc = &followparent_recalc,
1513};
1514
1515static struct clk fshostusb_fck = {
1516 .name = "fshostusb_fck",
1517 .ops = &clkops_omap2_dflt_wait,
1518 .parent = &core_48m_fck,
1519 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1520 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1521 .recalc = &followparent_recalc,
1522};
1523
1524/* CORE_12M_FCK based clocks */
1525
1526static struct clk core_12m_fck = {
1527 .name = "core_12m_fck",
1528 .ops = &clkops_null,
1529 .parent = &omap_12m_fck,
1530 .clkdm_name = "core_l4_clkdm",
1531 .recalc = &followparent_recalc,
1532};
1533
1534static struct clk hdq_fck = {
1535 .name = "hdq_fck",
1536 .ops = &clkops_omap2_dflt_wait,
1537 .parent = &core_12m_fck,
1538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1540 .recalc = &followparent_recalc,
1541};
1542
1543/* DPLL3-derived clock */
1544
1545static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1546 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1547 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1548 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1549 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1550 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1551 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1552 { .div = 0 }
1553};
1554
1555static const struct clksel ssi_ssr_clksel[] = {
1556 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1557 { .parent = NULL }
1558};
1559
1560static struct clk ssi_ssr_fck_3430es1 = {
1561 .name = "ssi_ssr_fck",
1562 .ops = &clkops_omap2_dflt,
1563 .init = &omap2_init_clksel_parent,
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1566 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1567 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1568 .clksel = ssi_ssr_clksel,
1569 .clkdm_name = "core_l4_clkdm",
1570 .recalc = &omap2_clksel_recalc,
1571};
1572
1573static struct clk ssi_ssr_fck_3430es2 = {
1574 .name = "ssi_ssr_fck",
1575 .ops = &clkops_omap3430es2_ssi_wait,
1576 .init = &omap2_init_clksel_parent,
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1578 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1579 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1580 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1581 .clksel = ssi_ssr_clksel,
1582 .clkdm_name = "core_l4_clkdm",
1583 .recalc = &omap2_clksel_recalc,
1584};
1585
1586static struct clk ssi_sst_fck_3430es1 = {
1587 .name = "ssi_sst_fck",
1588 .ops = &clkops_null,
1589 .parent = &ssi_ssr_fck_3430es1,
1590 .fixed_div = 2,
1591 .recalc = &omap2_fixed_divisor_recalc,
1592};
1593
1594static struct clk ssi_sst_fck_3430es2 = {
1595 .name = "ssi_sst_fck",
1596 .ops = &clkops_null,
1597 .parent = &ssi_ssr_fck_3430es2,
1598 .fixed_div = 2,
1599 .recalc = &omap2_fixed_divisor_recalc,
1600};
1601
1602
1603
1604/* CORE_L3_ICK based clocks */
1605
1606/*
1607 * XXX must add clk_enable/clk_disable for these if standard code won't
1608 * handle it
1609 */
1610static struct clk core_l3_ick = {
1611 .name = "core_l3_ick",
1612 .ops = &clkops_null,
1613 .parent = &l3_ick,
1614 .clkdm_name = "core_l3_clkdm",
1615 .recalc = &followparent_recalc,
1616};
1617
1618static struct clk hsotgusb_ick_3430es1 = {
1619 .name = "hsotgusb_ick",
1620 .ops = &clkops_omap2_dflt,
1621 .parent = &core_l3_ick,
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1624 .clkdm_name = "core_l3_clkdm",
1625 .recalc = &followparent_recalc,
1626};
1627
1628static struct clk hsotgusb_ick_3430es2 = {
1629 .name = "hsotgusb_ick",
1630 .ops = &clkops_omap3430es2_hsotgusb_wait,
1631 .parent = &core_l3_ick,
1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1633 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1634 .clkdm_name = "core_l3_clkdm",
1635 .recalc = &followparent_recalc,
1636};
1637
1638static struct clk sdrc_ick = {
1639 .name = "sdrc_ick",
1640 .ops = &clkops_omap2_dflt_wait,
1641 .parent = &core_l3_ick,
1642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1643 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1644 .flags = ENABLE_ON_INIT,
1645 .clkdm_name = "core_l3_clkdm",
1646 .recalc = &followparent_recalc,
1647};
1648
1649static struct clk gpmc_fck = {
1650 .name = "gpmc_fck",
1651 .ops = &clkops_null,
1652 .parent = &core_l3_ick,
1653 .flags = ENABLE_ON_INIT, /* huh? */
1654 .clkdm_name = "core_l3_clkdm",
1655 .recalc = &followparent_recalc,
1656};
1657
1658/* SECURITY_L3_ICK based clocks */
1659
1660static struct clk security_l3_ick = {
1661 .name = "security_l3_ick",
1662 .ops = &clkops_null,
1663 .parent = &l3_ick,
1664 .recalc = &followparent_recalc,
1665};
1666
1667static struct clk pka_ick = {
1668 .name = "pka_ick",
1669 .ops = &clkops_omap2_dflt_wait,
1670 .parent = &security_l3_ick,
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1672 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1673 .recalc = &followparent_recalc,
1674};
1675
1676/* CORE_L4_ICK based clocks */
1677
1678static struct clk core_l4_ick = {
1679 .name = "core_l4_ick",
1680 .ops = &clkops_null,
1681 .parent = &l4_ick,
1682 .clkdm_name = "core_l4_clkdm",
1683 .recalc = &followparent_recalc,
1684};
1685
1686static struct clk usbtll_ick = {
1687 .name = "usbtll_ick",
1688 .ops = &clkops_omap2_dflt_wait,
1689 .parent = &core_l4_ick,
1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1691 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1692 .clkdm_name = "core_l4_clkdm",
1693 .recalc = &followparent_recalc,
1694};
1695
1696static struct clk mmchs3_ick = {
1697 .name = "mmchs_ick",
1698 .ops = &clkops_omap2_dflt_wait,
1699 .id = 2,
1700 .parent = &core_l4_ick,
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1703 .clkdm_name = "core_l4_clkdm",
1704 .recalc = &followparent_recalc,
1705};
1706
1707/* Intersystem Communication Registers - chassis mode only */
1708static struct clk icr_ick = {
1709 .name = "icr_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1711 .parent = &core_l4_ick,
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1714 .clkdm_name = "core_l4_clkdm",
1715 .recalc = &followparent_recalc,
1716};
1717
1718static struct clk aes2_ick = {
1719 .name = "aes2_ick",
1720 .ops = &clkops_omap2_dflt_wait,
1721 .parent = &core_l4_ick,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1724 .clkdm_name = "core_l4_clkdm",
1725 .recalc = &followparent_recalc,
1726};
1727
1728static struct clk sha12_ick = {
1729 .name = "sha12_ick",
1730 .ops = &clkops_omap2_dflt_wait,
1731 .parent = &core_l4_ick,
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1734 .clkdm_name = "core_l4_clkdm",
1735 .recalc = &followparent_recalc,
1736};
1737
1738static struct clk des2_ick = {
1739 .name = "des2_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1741 .parent = &core_l4_ick,
1742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1743 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1744 .clkdm_name = "core_l4_clkdm",
1745 .recalc = &followparent_recalc,
1746};
1747
1748static struct clk mmchs2_ick = {
1749 .name = "mmchs_ick",
1750 .ops = &clkops_omap2_dflt_wait,
1751 .id = 1,
1752 .parent = &core_l4_ick,
1753 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1754 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1755 .clkdm_name = "core_l4_clkdm",
1756 .recalc = &followparent_recalc,
1757};
1758
1759static struct clk mmchs1_ick = {
1760 .name = "mmchs_ick",
1761 .ops = &clkops_omap2_dflt_wait,
1762 .parent = &core_l4_ick,
1763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1764 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1765 .clkdm_name = "core_l4_clkdm",
1766 .recalc = &followparent_recalc,
1767};
1768
1769static struct clk mspro_ick = {
1770 .name = "mspro_ick",
1771 .ops = &clkops_omap2_dflt_wait,
1772 .parent = &core_l4_ick,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1774 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1775 .clkdm_name = "core_l4_clkdm",
1776 .recalc = &followparent_recalc,
1777};
1778
1779static struct clk hdq_ick = {
1780 .name = "hdq_ick",
1781 .ops = &clkops_omap2_dflt_wait,
1782 .parent = &core_l4_ick,
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1785 .clkdm_name = "core_l4_clkdm",
1786 .recalc = &followparent_recalc,
1787};
1788
1789static struct clk mcspi4_ick = {
1790 .name = "mcspi_ick",
1791 .ops = &clkops_omap2_dflt_wait,
1792 .id = 4,
1793 .parent = &core_l4_ick,
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1795 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1796 .clkdm_name = "core_l4_clkdm",
1797 .recalc = &followparent_recalc,
1798};
1799
1800static struct clk mcspi3_ick = {
1801 .name = "mcspi_ick",
1802 .ops = &clkops_omap2_dflt_wait,
1803 .id = 3,
1804 .parent = &core_l4_ick,
1805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1806 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1807 .clkdm_name = "core_l4_clkdm",
1808 .recalc = &followparent_recalc,
1809};
1810
1811static struct clk mcspi2_ick = {
1812 .name = "mcspi_ick",
1813 .ops = &clkops_omap2_dflt_wait,
1814 .id = 2,
1815 .parent = &core_l4_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1818 .clkdm_name = "core_l4_clkdm",
1819 .recalc = &followparent_recalc,
1820};
1821
1822static struct clk mcspi1_ick = {
1823 .name = "mcspi_ick",
1824 .ops = &clkops_omap2_dflt_wait,
1825 .id = 1,
1826 .parent = &core_l4_ick,
1827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1829 .clkdm_name = "core_l4_clkdm",
1830 .recalc = &followparent_recalc,
1831};
1832
1833static struct clk i2c3_ick = {
1834 .name = "i2c_ick",
1835 .ops = &clkops_omap2_dflt_wait,
1836 .id = 3,
1837 .parent = &core_l4_ick,
1838 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1840 .clkdm_name = "core_l4_clkdm",
1841 .recalc = &followparent_recalc,
1842};
1843
1844static struct clk i2c2_ick = {
1845 .name = "i2c_ick",
1846 .ops = &clkops_omap2_dflt_wait,
1847 .id = 2,
1848 .parent = &core_l4_ick,
1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1851 .clkdm_name = "core_l4_clkdm",
1852 .recalc = &followparent_recalc,
1853};
1854
1855static struct clk i2c1_ick = {
1856 .name = "i2c_ick",
1857 .ops = &clkops_omap2_dflt_wait,
1858 .id = 1,
1859 .parent = &core_l4_ick,
1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1862 .clkdm_name = "core_l4_clkdm",
1863 .recalc = &followparent_recalc,
1864};
1865
1866static struct clk uart2_ick = {
1867 .name = "uart2_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1869 .parent = &core_l4_ick,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1872 .clkdm_name = "core_l4_clkdm",
1873 .recalc = &followparent_recalc,
1874};
1875
1876static struct clk uart1_ick = {
1877 .name = "uart1_ick",
1878 .ops = &clkops_omap2_dflt_wait,
1879 .parent = &core_l4_ick,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1882 .clkdm_name = "core_l4_clkdm",
1883 .recalc = &followparent_recalc,
1884};
1885
1886static struct clk gpt11_ick = {
1887 .name = "gpt11_ick",
1888 .ops = &clkops_omap2_dflt_wait,
1889 .parent = &core_l4_ick,
1890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1892 .clkdm_name = "core_l4_clkdm",
1893 .recalc = &followparent_recalc,
1894};
1895
1896static struct clk gpt10_ick = {
1897 .name = "gpt10_ick",
1898 .ops = &clkops_omap2_dflt_wait,
1899 .parent = &core_l4_ick,
1900 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1902 .clkdm_name = "core_l4_clkdm",
1903 .recalc = &followparent_recalc,
1904};
1905
1906static struct clk mcbsp5_ick = {
1907 .name = "mcbsp_ick",
1908 .ops = &clkops_omap2_dflt_wait,
1909 .id = 5,
1910 .parent = &core_l4_ick,
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk mcbsp1_ick = {
1918 .name = "mcbsp_ick",
1919 .ops = &clkops_omap2_dflt_wait,
1920 .id = 1,
1921 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1924 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc,
1926};
1927
1928static struct clk fac_ick = {
1929 .name = "fac_ick",
1930 .ops = &clkops_omap2_dflt_wait,
1931 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1934 .clkdm_name = "core_l4_clkdm",
1935 .recalc = &followparent_recalc,
1936};
1937
1938static struct clk mailboxes_ick = {
1939 .name = "mailboxes_ick",
1940 .ops = &clkops_omap2_dflt_wait,
1941 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1944 .clkdm_name = "core_l4_clkdm",
1945 .recalc = &followparent_recalc,
1946};
1947
1948static struct clk omapctrl_ick = {
1949 .name = "omapctrl_ick",
1950 .ops = &clkops_omap2_dflt_wait,
1951 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1954 .flags = ENABLE_ON_INIT,
1955 .recalc = &followparent_recalc,
1956};
1957
1958/* SSI_L4_ICK based clocks */
1959
1960static struct clk ssi_l4_ick = {
1961 .name = "ssi_l4_ick",
1962 .ops = &clkops_null,
1963 .parent = &l4_ick,
1964 .clkdm_name = "core_l4_clkdm",
1965 .recalc = &followparent_recalc,
1966};
1967
1968static struct clk ssi_ick_3430es1 = {
1969 .name = "ssi_ick",
1970 .ops = &clkops_omap2_dflt,
1971 .parent = &ssi_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1974 .clkdm_name = "core_l4_clkdm",
1975 .recalc = &followparent_recalc,
1976};
1977
1978static struct clk ssi_ick_3430es2 = {
1979 .name = "ssi_ick",
1980 .ops = &clkops_omap3430es2_ssi_wait,
1981 .parent = &ssi_l4_ick,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1984 .clkdm_name = "core_l4_clkdm",
1985 .recalc = &followparent_recalc,
1986};
1987
1988/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1989 * but l4_ick makes more sense to me */
1990
1991static const struct clksel usb_l4_clksel[] = {
1992 { .parent = &l4_ick, .rates = div2_rates },
1993 { .parent = NULL },
1994};
1995
1996static struct clk usb_l4_ick = {
1997 .name = "usb_l4_ick",
1998 .ops = &clkops_omap2_dflt_wait,
1999 .parent = &l4_ick,
2000 .init = &omap2_init_clksel_parent,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2003 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2004 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2005 .clksel = usb_l4_clksel,
2006 .recalc = &omap2_clksel_recalc,
2007};
2008
2009/* SECURITY_L4_ICK2 based clocks */
2010
2011static struct clk security_l4_ick2 = {
2012 .name = "security_l4_ick2",
2013 .ops = &clkops_null,
2014 .parent = &l4_ick,
2015 .recalc = &followparent_recalc,
2016};
2017
2018static struct clk aes1_ick = {
2019 .name = "aes1_ick",
2020 .ops = &clkops_omap2_dflt_wait,
2021 .parent = &security_l4_ick2,
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2023 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2024 .recalc = &followparent_recalc,
2025};
2026
2027static struct clk rng_ick = {
2028 .name = "rng_ick",
2029 .ops = &clkops_omap2_dflt_wait,
2030 .parent = &security_l4_ick2,
2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2032 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2033 .recalc = &followparent_recalc,
2034};
2035
2036static struct clk sha11_ick = {
2037 .name = "sha11_ick",
2038 .ops = &clkops_omap2_dflt_wait,
2039 .parent = &security_l4_ick2,
2040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2041 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2042 .recalc = &followparent_recalc,
2043};
2044
2045static struct clk des1_ick = {
2046 .name = "des1_ick",
2047 .ops = &clkops_omap2_dflt_wait,
2048 .parent = &security_l4_ick2,
2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2050 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2051 .recalc = &followparent_recalc,
2052};
2053
2054/* DSS */
2055static struct clk dss1_alwon_fck_3430es1 = {
2056 .name = "dss1_alwon_fck",
2057 .ops = &clkops_omap2_dflt,
2058 .parent = &dpll4_m4x2_ck,
2059 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2060 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2061 .clkdm_name = "dss_clkdm",
2062 .recalc = &followparent_recalc,
2063};
2064
2065static struct clk dss1_alwon_fck_3430es2 = {
2066 .name = "dss1_alwon_fck",
2067 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2068 .parent = &dpll4_m4x2_ck,
2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2070 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2071 .clkdm_name = "dss_clkdm",
2072 .recalc = &followparent_recalc,
2073};
2074
2075static struct clk dss_tv_fck = {
2076 .name = "dss_tv_fck",
2077 .ops = &clkops_omap2_dflt,
2078 .parent = &omap_54m_fck,
2079 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP3430_EN_TV_SHIFT,
2081 .clkdm_name = "dss_clkdm",
2082 .recalc = &followparent_recalc,
2083};
2084
2085static struct clk dss_96m_fck = {
2086 .name = "dss_96m_fck",
2087 .ops = &clkops_omap2_dflt,
2088 .parent = &omap_96m_fck,
2089 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2090 .enable_bit = OMAP3430_EN_TV_SHIFT,
2091 .clkdm_name = "dss_clkdm",
2092 .recalc = &followparent_recalc,
2093};
2094
2095static struct clk dss2_alwon_fck = {
2096 .name = "dss2_alwon_fck",
2097 .ops = &clkops_omap2_dflt,
2098 .parent = &sys_ck,
2099 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2100 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2101 .clkdm_name = "dss_clkdm",
2102 .recalc = &followparent_recalc,
2103};
2104
2105static struct clk dss_ick_3430es1 = {
2106 /* Handles both L3 and L4 clocks */
2107 .name = "dss_ick",
2108 .ops = &clkops_omap2_dflt,
2109 .parent = &l4_ick,
2110 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2111 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2112 .clkdm_name = "dss_clkdm",
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk dss_ick_3430es2 = {
2117 /* Handles both L3 and L4 clocks */
2118 .name = "dss_ick",
2119 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2120 .parent = &l4_ick,
2121 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2122 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2123 .clkdm_name = "dss_clkdm",
2124 .recalc = &followparent_recalc,
2125};
2126
2127/* CAM */
2128
2129static struct clk cam_mclk = {
2130 .name = "cam_mclk",
2131 .ops = &clkops_omap2_dflt,
2132 .parent = &dpll4_m5x2_ck,
2133 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2134 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2135 .clkdm_name = "cam_clkdm",
2136 .recalc = &followparent_recalc,
2137};
2138
2139static struct clk cam_ick = {
2140 /* Handles both L3 and L4 clocks */
2141 .name = "cam_ick",
2142 .ops = &clkops_omap2_dflt,
2143 .parent = &l4_ick,
2144 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2145 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2146 .clkdm_name = "cam_clkdm",
2147 .recalc = &followparent_recalc,
2148};
2149
2150static struct clk csi2_96m_fck = {
2151 .name = "csi2_96m_fck",
2152 .ops = &clkops_omap2_dflt,
2153 .parent = &core_96m_fck,
2154 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2155 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2156 .clkdm_name = "cam_clkdm",
2157 .recalc = &followparent_recalc,
2158};
2159
2160/* USBHOST - 3430ES2 only */
2161
2162static struct clk usbhost_120m_fck = {
2163 .name = "usbhost_120m_fck",
2164 .ops = &clkops_omap2_dflt,
2165 .parent = &dpll5_m2_ck,
2166 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2167 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2168 .clkdm_name = "usbhost_clkdm",
2169 .recalc = &followparent_recalc,
2170};
2171
2172static struct clk usbhost_48m_fck = {
2173 .name = "usbhost_48m_fck",
2174 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2175 .parent = &omap_48m_fck,
2176 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2177 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2178 .clkdm_name = "usbhost_clkdm",
2179 .recalc = &followparent_recalc,
2180};
2181
2182static struct clk usbhost_ick = {
2183 /* Handles both L3 and L4 clocks */
2184 .name = "usbhost_ick",
2185 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2186 .parent = &l4_ick,
2187 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2188 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2189 .clkdm_name = "usbhost_clkdm",
2190 .recalc = &followparent_recalc,
2191};
2192
2193/* WKUP */
2194
2195static const struct clksel_rate usim_96m_rates[] = {
2196 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2197 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2198 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2199 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2200 { .div = 0 },
2201};
2202
2203static const struct clksel_rate usim_120m_rates[] = {
2204 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2205 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2206 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2207 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2208 { .div = 0 },
2209};
2210
2211static const struct clksel usim_clksel[] = {
2212 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2213 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2214 { .parent = &sys_ck, .rates = div2_rates },
2215 { .parent = NULL },
2216};
2217
2218/* 3430ES2 only */
2219static struct clk usim_fck = {
2220 .name = "usim_fck",
2221 .ops = &clkops_omap2_dflt_wait,
2222 .init = &omap2_init_clksel_parent,
2223 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2224 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2225 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2226 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2227 .clksel = usim_clksel,
2228 .recalc = &omap2_clksel_recalc,
2229};
2230
2231/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2232static struct clk gpt1_fck = {
2233 .name = "gpt1_fck",
2234 .ops = &clkops_omap2_dflt_wait,
2235 .init = &omap2_init_clksel_parent,
2236 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2237 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2238 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2239 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2240 .clksel = omap343x_gpt_clksel,
2241 .clkdm_name = "wkup_clkdm",
2242 .recalc = &omap2_clksel_recalc,
2243};
2244
2245static struct clk wkup_32k_fck = {
2246 .name = "wkup_32k_fck",
2247 .ops = &clkops_null,
2248 .parent = &omap_32k_fck,
2249 .clkdm_name = "wkup_clkdm",
2250 .recalc = &followparent_recalc,
2251};
2252
2253static struct clk gpio1_dbck = {
2254 .name = "gpio1_dbck",
2255 .ops = &clkops_omap2_dflt,
2256 .parent = &wkup_32k_fck,
2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2258 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2259 .clkdm_name = "wkup_clkdm",
2260 .recalc = &followparent_recalc,
2261};
2262
2263static struct clk wdt2_fck = {
2264 .name = "wdt2_fck",
2265 .ops = &clkops_omap2_dflt_wait,
2266 .parent = &wkup_32k_fck,
2267 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2268 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2269 .clkdm_name = "wkup_clkdm",
2270 .recalc = &followparent_recalc,
2271};
2272
2273static struct clk wkup_l4_ick = {
2274 .name = "wkup_l4_ick",
2275 .ops = &clkops_null,
2276 .parent = &sys_ck,
2277 .clkdm_name = "wkup_clkdm",
2278 .recalc = &followparent_recalc,
2279};
2280
2281/* 3430ES2 only */
2282/* Never specifically named in the TRM, so we have to infer a likely name */
2283static struct clk usim_ick = {
2284 .name = "usim_ick",
2285 .ops = &clkops_omap2_dflt_wait,
2286 .parent = &wkup_l4_ick,
2287 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2288 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2289 .clkdm_name = "wkup_clkdm",
2290 .recalc = &followparent_recalc,
2291};
2292
2293static struct clk wdt2_ick = {
2294 .name = "wdt2_ick",
2295 .ops = &clkops_omap2_dflt_wait,
2296 .parent = &wkup_l4_ick,
2297 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2298 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2299 .clkdm_name = "wkup_clkdm",
2300 .recalc = &followparent_recalc,
2301};
2302
2303static struct clk wdt1_ick = {
2304 .name = "wdt1_ick",
2305 .ops = &clkops_omap2_dflt_wait,
2306 .parent = &wkup_l4_ick,
2307 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2308 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2309 .clkdm_name = "wkup_clkdm",
2310 .recalc = &followparent_recalc,
2311};
2312
2313static struct clk gpio1_ick = {
2314 .name = "gpio1_ick",
2315 .ops = &clkops_omap2_dflt_wait,
2316 .parent = &wkup_l4_ick,
2317 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2318 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2319 .clkdm_name = "wkup_clkdm",
2320 .recalc = &followparent_recalc,
2321};
2322
2323static struct clk omap_32ksync_ick = {
2324 .name = "omap_32ksync_ick",
2325 .ops = &clkops_omap2_dflt_wait,
2326 .parent = &wkup_l4_ick,
2327 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2328 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2329 .clkdm_name = "wkup_clkdm",
2330 .recalc = &followparent_recalc,
2331};
2332
2333/* XXX This clock no longer exists in 3430 TRM rev F */
2334static struct clk gpt12_ick = {
2335 .name = "gpt12_ick",
2336 .ops = &clkops_omap2_dflt_wait,
2337 .parent = &wkup_l4_ick,
2338 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2339 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2340 .clkdm_name = "wkup_clkdm",
2341 .recalc = &followparent_recalc,
2342};
2343
2344static struct clk gpt1_ick = {
2345 .name = "gpt1_ick",
2346 .ops = &clkops_omap2_dflt_wait,
2347 .parent = &wkup_l4_ick,
2348 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2349 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2350 .clkdm_name = "wkup_clkdm",
2351 .recalc = &followparent_recalc,
2352};
2353
2354
2355
2356/* PER clock domain */
2357
2358static struct clk per_96m_fck = {
2359 .name = "per_96m_fck",
2360 .ops = &clkops_null,
2361 .parent = &omap_96m_alwon_fck,
2362 .clkdm_name = "per_clkdm",
2363 .recalc = &followparent_recalc,
2364};
2365
2366static struct clk per_48m_fck = {
2367 .name = "per_48m_fck",
2368 .ops = &clkops_null,
2369 .parent = &omap_48m_fck,
2370 .clkdm_name = "per_clkdm",
2371 .recalc = &followparent_recalc,
2372};
2373
2374static struct clk uart3_fck = {
2375 .name = "uart3_fck",
2376 .ops = &clkops_omap2_dflt_wait,
2377 .parent = &per_48m_fck,
2378 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2379 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2380 .clkdm_name = "per_clkdm",
2381 .recalc = &followparent_recalc,
2382};
2383
2384static struct clk gpt2_fck = {
2385 .name = "gpt2_fck",
2386 .ops = &clkops_omap2_dflt_wait,
2387 .init = &omap2_init_clksel_parent,
2388 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2389 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2390 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2391 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2392 .clksel = omap343x_gpt_clksel,
2393 .clkdm_name = "per_clkdm",
2394 .recalc = &omap2_clksel_recalc,
2395};
2396
2397static struct clk gpt3_fck = {
2398 .name = "gpt3_fck",
2399 .ops = &clkops_omap2_dflt_wait,
2400 .init = &omap2_init_clksel_parent,
2401 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2402 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2403 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2404 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2405 .clksel = omap343x_gpt_clksel,
2406 .clkdm_name = "per_clkdm",
2407 .recalc = &omap2_clksel_recalc,
2408};
2409
2410static struct clk gpt4_fck = {
2411 .name = "gpt4_fck",
2412 .ops = &clkops_omap2_dflt_wait,
2413 .init = &omap2_init_clksel_parent,
2414 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2415 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2416 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2417 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2418 .clksel = omap343x_gpt_clksel,
2419 .clkdm_name = "per_clkdm",
2420 .recalc = &omap2_clksel_recalc,
2421};
2422
2423static struct clk gpt5_fck = {
2424 .name = "gpt5_fck",
2425 .ops = &clkops_omap2_dflt_wait,
2426 .init = &omap2_init_clksel_parent,
2427 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2428 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2429 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2430 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2431 .clksel = omap343x_gpt_clksel,
2432 .clkdm_name = "per_clkdm",
2433 .recalc = &omap2_clksel_recalc,
2434};
2435
2436static struct clk gpt6_fck = {
2437 .name = "gpt6_fck",
2438 .ops = &clkops_omap2_dflt_wait,
2439 .init = &omap2_init_clksel_parent,
2440 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2442 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2443 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2444 .clksel = omap343x_gpt_clksel,
2445 .clkdm_name = "per_clkdm",
2446 .recalc = &omap2_clksel_recalc,
2447};
2448
2449static struct clk gpt7_fck = {
2450 .name = "gpt7_fck",
2451 .ops = &clkops_omap2_dflt_wait,
2452 .init = &omap2_init_clksel_parent,
2453 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2454 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2455 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2456 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2457 .clksel = omap343x_gpt_clksel,
2458 .clkdm_name = "per_clkdm",
2459 .recalc = &omap2_clksel_recalc,
2460};
2461
2462static struct clk gpt8_fck = {
2463 .name = "gpt8_fck",
2464 .ops = &clkops_omap2_dflt_wait,
2465 .init = &omap2_init_clksel_parent,
2466 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2467 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2468 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2469 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2470 .clksel = omap343x_gpt_clksel,
2471 .clkdm_name = "per_clkdm",
2472 .recalc = &omap2_clksel_recalc,
2473};
2474
2475static struct clk gpt9_fck = {
2476 .name = "gpt9_fck",
2477 .ops = &clkops_omap2_dflt_wait,
2478 .init = &omap2_init_clksel_parent,
2479 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2481 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2482 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2483 .clksel = omap343x_gpt_clksel,
2484 .clkdm_name = "per_clkdm",
2485 .recalc = &omap2_clksel_recalc,
2486};
2487
2488static struct clk per_32k_alwon_fck = {
2489 .name = "per_32k_alwon_fck",
2490 .ops = &clkops_null,
2491 .parent = &omap_32k_fck,
2492 .clkdm_name = "per_clkdm",
2493 .recalc = &followparent_recalc,
2494};
2495
2496static struct clk gpio6_dbck = {
2497 .name = "gpio6_dbck",
2498 .ops = &clkops_omap2_dflt,
2499 .parent = &per_32k_alwon_fck,
2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2501 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2502 .clkdm_name = "per_clkdm",
2503 .recalc = &followparent_recalc,
2504};
2505
2506static struct clk gpio5_dbck = {
2507 .name = "gpio5_dbck",
2508 .ops = &clkops_omap2_dflt,
2509 .parent = &per_32k_alwon_fck,
2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2511 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2512 .clkdm_name = "per_clkdm",
2513 .recalc = &followparent_recalc,
2514};
2515
2516static struct clk gpio4_dbck = {
2517 .name = "gpio4_dbck",
2518 .ops = &clkops_omap2_dflt,
2519 .parent = &per_32k_alwon_fck,
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2521 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2522 .clkdm_name = "per_clkdm",
2523 .recalc = &followparent_recalc,
2524};
2525
2526static struct clk gpio3_dbck = {
2527 .name = "gpio3_dbck",
2528 .ops = &clkops_omap2_dflt,
2529 .parent = &per_32k_alwon_fck,
2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2531 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2532 .clkdm_name = "per_clkdm",
2533 .recalc = &followparent_recalc,
2534};
2535
2536static struct clk gpio2_dbck = {
2537 .name = "gpio2_dbck",
2538 .ops = &clkops_omap2_dflt,
2539 .parent = &per_32k_alwon_fck,
2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2541 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2542 .clkdm_name = "per_clkdm",
2543 .recalc = &followparent_recalc,
2544};
2545
2546static struct clk wdt3_fck = {
2547 .name = "wdt3_fck",
2548 .ops = &clkops_omap2_dflt_wait,
2549 .parent = &per_32k_alwon_fck,
2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2552 .clkdm_name = "per_clkdm",
2553 .recalc = &followparent_recalc,
2554};
2555
2556static struct clk per_l4_ick = {
2557 .name = "per_l4_ick",
2558 .ops = &clkops_null,
2559 .parent = &l4_ick,
2560 .clkdm_name = "per_clkdm",
2561 .recalc = &followparent_recalc,
2562};
2563
2564static struct clk gpio6_ick = {
2565 .name = "gpio6_ick",
2566 .ops = &clkops_omap2_dflt_wait,
2567 .parent = &per_l4_ick,
2568 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2569 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2570 .clkdm_name = "per_clkdm",
2571 .recalc = &followparent_recalc,
2572};
2573
2574static struct clk gpio5_ick = {
2575 .name = "gpio5_ick",
2576 .ops = &clkops_omap2_dflt_wait,
2577 .parent = &per_l4_ick,
2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2579 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2580 .clkdm_name = "per_clkdm",
2581 .recalc = &followparent_recalc,
2582};
2583
2584static struct clk gpio4_ick = {
2585 .name = "gpio4_ick",
2586 .ops = &clkops_omap2_dflt_wait,
2587 .parent = &per_l4_ick,
2588 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2589 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2590 .clkdm_name = "per_clkdm",
2591 .recalc = &followparent_recalc,
2592};
2593
2594static struct clk gpio3_ick = {
2595 .name = "gpio3_ick",
2596 .ops = &clkops_omap2_dflt_wait,
2597 .parent = &per_l4_ick,
2598 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2599 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2600 .clkdm_name = "per_clkdm",
2601 .recalc = &followparent_recalc,
2602};
2603
2604static struct clk gpio2_ick = {
2605 .name = "gpio2_ick",
2606 .ops = &clkops_omap2_dflt_wait,
2607 .parent = &per_l4_ick,
2608 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2609 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2610 .clkdm_name = "per_clkdm",
2611 .recalc = &followparent_recalc,
2612};
2613
2614static struct clk wdt3_ick = {
2615 .name = "wdt3_ick",
2616 .ops = &clkops_omap2_dflt_wait,
2617 .parent = &per_l4_ick,
2618 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2619 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2620 .clkdm_name = "per_clkdm",
2621 .recalc = &followparent_recalc,
2622};
2623
2624static struct clk uart3_ick = {
2625 .name = "uart3_ick",
2626 .ops = &clkops_omap2_dflt_wait,
2627 .parent = &per_l4_ick,
2628 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2629 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2630 .clkdm_name = "per_clkdm",
2631 .recalc = &followparent_recalc,
2632};
2633
2634static struct clk gpt9_ick = {
2635 .name = "gpt9_ick",
2636 .ops = &clkops_omap2_dflt_wait,
2637 .parent = &per_l4_ick,
2638 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2639 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2640 .clkdm_name = "per_clkdm",
2641 .recalc = &followparent_recalc,
2642};
2643
2644static struct clk gpt8_ick = {
2645 .name = "gpt8_ick",
2646 .ops = &clkops_omap2_dflt_wait,
2647 .parent = &per_l4_ick,
2648 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2649 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2650 .clkdm_name = "per_clkdm",
2651 .recalc = &followparent_recalc,
2652};
2653
2654static struct clk gpt7_ick = {
2655 .name = "gpt7_ick",
2656 .ops = &clkops_omap2_dflt_wait,
2657 .parent = &per_l4_ick,
2658 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2659 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2660 .clkdm_name = "per_clkdm",
2661 .recalc = &followparent_recalc,
2662};
2663
2664static struct clk gpt6_ick = {
2665 .name = "gpt6_ick",
2666 .ops = &clkops_omap2_dflt_wait,
2667 .parent = &per_l4_ick,
2668 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2670 .clkdm_name = "per_clkdm",
2671 .recalc = &followparent_recalc,
2672};
2673
2674static struct clk gpt5_ick = {
2675 .name = "gpt5_ick",
2676 .ops = &clkops_omap2_dflt_wait,
2677 .parent = &per_l4_ick,
2678 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2680 .clkdm_name = "per_clkdm",
2681 .recalc = &followparent_recalc,
2682};
2683
2684static struct clk gpt4_ick = {
2685 .name = "gpt4_ick",
2686 .ops = &clkops_omap2_dflt_wait,
2687 .parent = &per_l4_ick,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2690 .clkdm_name = "per_clkdm",
2691 .recalc = &followparent_recalc,
2692};
2693
2694static struct clk gpt3_ick = {
2695 .name = "gpt3_ick",
2696 .ops = &clkops_omap2_dflt_wait,
2697 .parent = &per_l4_ick,
2698 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2700 .clkdm_name = "per_clkdm",
2701 .recalc = &followparent_recalc,
2702};
2703
2704static struct clk gpt2_ick = {
2705 .name = "gpt2_ick",
2706 .ops = &clkops_omap2_dflt_wait,
2707 .parent = &per_l4_ick,
2708 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2710 .clkdm_name = "per_clkdm",
2711 .recalc = &followparent_recalc,
2712};
2713
2714static struct clk mcbsp2_ick = {
2715 .name = "mcbsp_ick",
2716 .ops = &clkops_omap2_dflt_wait,
2717 .id = 2,
2718 .parent = &per_l4_ick,
2719 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2720 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2721 .clkdm_name = "per_clkdm",
2722 .recalc = &followparent_recalc,
2723};
2724
2725static struct clk mcbsp3_ick = {
2726 .name = "mcbsp_ick",
2727 .ops = &clkops_omap2_dflt_wait,
2728 .id = 3,
2729 .parent = &per_l4_ick,
2730 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2732 .clkdm_name = "per_clkdm",
2733 .recalc = &followparent_recalc,
2734};
2735
2736static struct clk mcbsp4_ick = {
2737 .name = "mcbsp_ick",
2738 .ops = &clkops_omap2_dflt_wait,
2739 .id = 4,
2740 .parent = &per_l4_ick,
2741 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2743 .clkdm_name = "per_clkdm",
2744 .recalc = &followparent_recalc,
2745};
2746
2747static const struct clksel mcbsp_234_clksel[] = {
2748 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2749 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2750 { .parent = NULL }
2751};
2752
2753static struct clk mcbsp2_fck = {
2754 .name = "mcbsp_fck",
2755 .ops = &clkops_omap2_dflt_wait,
2756 .id = 2,
2757 .init = &omap2_init_clksel_parent,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2759 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2760 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2761 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2762 .clksel = mcbsp_234_clksel,
2763 .clkdm_name = "per_clkdm",
2764 .recalc = &omap2_clksel_recalc,
2765};
2766
2767static struct clk mcbsp3_fck = {
2768 .name = "mcbsp_fck",
2769 .ops = &clkops_omap2_dflt_wait,
2770 .id = 3,
2771 .init = &omap2_init_clksel_parent,
2772 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2773 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2774 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2775 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2776 .clksel = mcbsp_234_clksel,
2777 .clkdm_name = "per_clkdm",
2778 .recalc = &omap2_clksel_recalc,
2779};
2780
2781static struct clk mcbsp4_fck = {
2782 .name = "mcbsp_fck",
2783 .ops = &clkops_omap2_dflt_wait,
2784 .id = 4,
2785 .init = &omap2_init_clksel_parent,
2786 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2787 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2788 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2789 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2790 .clksel = mcbsp_234_clksel,
2791 .clkdm_name = "per_clkdm",
2792 .recalc = &omap2_clksel_recalc,
2793};
2794
2795/* EMU clocks */
2796
2797/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2798
2799static const struct clksel_rate emu_src_sys_rates[] = {
2800 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2801 { .div = 0 },
2802};
2803
2804static const struct clksel_rate emu_src_core_rates[] = {
2805 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2806 { .div = 0 },
2807};
2808
2809static const struct clksel_rate emu_src_per_rates[] = {
2810 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2811 { .div = 0 },
2812};
2813
2814static const struct clksel_rate emu_src_mpu_rates[] = {
2815 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2816 { .div = 0 },
2817};
2818
2819static const struct clksel emu_src_clksel[] = {
2820 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2821 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2822 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2823 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2824 { .parent = NULL },
2825};
2826
2827/*
2828 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2829 * to switch the source of some of the EMU clocks.
2830 * XXX Are there CLKEN bits for these EMU clks?
2831 */
2832static struct clk emu_src_ck = {
2833 .name = "emu_src_ck",
2834 .ops = &clkops_null,
2835 .init = &omap2_init_clksel_parent,
2836 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2837 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2838 .clksel = emu_src_clksel,
2839 .clkdm_name = "emu_clkdm",
2840 .recalc = &omap2_clksel_recalc,
2841};
2842
2843static const struct clksel_rate pclk_emu_rates[] = {
2844 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2845 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2846 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2847 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2848 { .div = 0 },
2849};
2850
2851static const struct clksel pclk_emu_clksel[] = {
2852 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2853 { .parent = NULL },
2854};
2855
2856static struct clk pclk_fck = {
2857 .name = "pclk_fck",
2858 .ops = &clkops_null,
2859 .init = &omap2_init_clksel_parent,
2860 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2861 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2862 .clksel = pclk_emu_clksel,
2863 .clkdm_name = "emu_clkdm",
2864 .recalc = &omap2_clksel_recalc,
2865};
2866
2867static const struct clksel_rate pclkx2_emu_rates[] = {
2868 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2869 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2870 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2871 { .div = 0 },
2872};
2873
2874static const struct clksel pclkx2_emu_clksel[] = {
2875 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2876 { .parent = NULL },
2877};
2878
2879static struct clk pclkx2_fck = {
2880 .name = "pclkx2_fck",
2881 .ops = &clkops_null,
2882 .init = &omap2_init_clksel_parent,
2883 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2884 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2885 .clksel = pclkx2_emu_clksel,
2886 .clkdm_name = "emu_clkdm",
2887 .recalc = &omap2_clksel_recalc,
2888};
2889
2890static const struct clksel atclk_emu_clksel[] = {
2891 { .parent = &emu_src_ck, .rates = div2_rates },
2892 { .parent = NULL },
2893};
2894
2895static struct clk atclk_fck = {
2896 .name = "atclk_fck",
2897 .ops = &clkops_null,
2898 .init = &omap2_init_clksel_parent,
2899 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2900 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2901 .clksel = atclk_emu_clksel,
2902 .clkdm_name = "emu_clkdm",
2903 .recalc = &omap2_clksel_recalc,
2904};
2905
2906static struct clk traceclk_src_fck = {
2907 .name = "traceclk_src_fck",
2908 .ops = &clkops_null,
2909 .init = &omap2_init_clksel_parent,
2910 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2911 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2912 .clksel = emu_src_clksel,
2913 .clkdm_name = "emu_clkdm",
2914 .recalc = &omap2_clksel_recalc,
2915};
2916
2917static const struct clksel_rate traceclk_rates[] = {
2918 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2919 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2920 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2921 { .div = 0 },
2922};
2923
2924static const struct clksel traceclk_clksel[] = {
2925 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2926 { .parent = NULL },
2927};
2928
2929static struct clk traceclk_fck = {
2930 .name = "traceclk_fck",
2931 .ops = &clkops_null,
2932 .init = &omap2_init_clksel_parent,
2933 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2934 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2935 .clksel = traceclk_clksel,
2936 .clkdm_name = "emu_clkdm",
2937 .recalc = &omap2_clksel_recalc,
2938};
2939
2940/* SR clocks */
2941
2942/* SmartReflex fclk (VDD1) */
2943static struct clk sr1_fck = {
2944 .name = "sr1_fck",
2945 .ops = &clkops_omap2_dflt_wait,
2946 .parent = &sys_ck,
2947 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2948 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2949 .recalc = &followparent_recalc,
2950};
2951
2952/* SmartReflex fclk (VDD2) */
2953static struct clk sr2_fck = {
2954 .name = "sr2_fck",
2955 .ops = &clkops_omap2_dflt_wait,
2956 .parent = &sys_ck,
2957 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2958 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2959 .recalc = &followparent_recalc,
2960};
2961
2962static struct clk sr_l4_ick = {
2963 .name = "sr_l4_ick",
2964 .ops = &clkops_null, /* RMK: missing? */
2965 .parent = &l4_ick,
2966 .clkdm_name = "core_l4_clkdm",
2967 .recalc = &followparent_recalc,
2968};
2969
2970/* SECURE_32K_FCK clocks */
2971
2972static struct clk gpt12_fck = {
2973 .name = "gpt12_fck",
2974 .ops = &clkops_null,
2975 .parent = &secure_32k_fck,
2976 .recalc = &followparent_recalc,
2977};
2978
2979static struct clk wdt1_fck = {
2980 .name = "wdt1_fck",
2981 .ops = &clkops_null,
2982 .parent = &secure_32k_fck,
2983 .recalc = &followparent_recalc,
2984};
2985
2986
2987/*
2988 * clkdev
2989 */
2990
2991static struct omap_clk omap34xx_clks[] = {
2992 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
2993 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
2994 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
2995 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
2996 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
2997 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
2998 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
2999 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
3000 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
3001 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
3002 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
3003 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
3004 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
3005 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
3006 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
3007 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3008 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
3009 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
3010 CLK(NULL, "core_ck", &core_ck, CK_343X),
3011 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
3012 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
3013 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
3014 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
3015 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
3016 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
3017 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
3018 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
3019 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
3020 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
3021 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
3022 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
3023 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
3024 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
3025 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
3026 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
3027 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
3028 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
3029 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
3030 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
3031 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
3032 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
3033 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
3034 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
3035 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
3036 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
3037 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
3038 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
3039 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
3040 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
3041 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
3042 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
3043 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
3044 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
3045 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3046 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
3047 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
3048 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
3049 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
3050 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3051 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3052 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3053 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3054 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3055 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
3056 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
3057 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3058 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3059 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3060 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
3061 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
3062 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
3063 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
3064 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
3065 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
3066 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
3067 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
3068 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
3069 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
3070 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
3071 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
3072 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
3073 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
3074 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
3075 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
3076 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
3077 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
3078 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
3079 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
3080 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
3081 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
3082 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
3083 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3084 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
3085 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
3086 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3087 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3088 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3089 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
3090 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
3091 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3092 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
3093 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
3094 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
3095 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3096 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
3097 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
3098 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
3099 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
3100 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3101 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3102 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
3103 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
3104 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
3105 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
3106 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
3107 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
3108 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
3109 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
3110 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
3111 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
3112 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
3113 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
3114 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
3115 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
3116 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
3117 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
3118 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
3119 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
3120 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
3121 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3122 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
3123 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
3124 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3125 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3126 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3127 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3128 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3129 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3130 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3131 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3132 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3133 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3134 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
3135 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X),
3136 CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X),
3137 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X),
3138 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
3139 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2),
3140 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3141 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3142 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
3143 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
3144 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
3145 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
3146 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
3147 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
3148 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
3149 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
3150 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
3151 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3152 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
3153 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
3154 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
3155 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
3156 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
3157 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
3158 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
3159 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
3160 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
3161 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
3162 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
3163 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
3164 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
3165 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
3166 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
3167 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
3168 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
3169 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
3170 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
3171 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
3172 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
3173 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
3174 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
3175 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
3176 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
3177 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
3178 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
3179 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
3180 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
3181 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
3182 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
3183 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
3184 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
3185 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
3186 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
3187 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
3188 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
3189 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
3190 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
3191 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
3192 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
3193 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
3194 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
3195 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
3196 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
3197 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
3198 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
3199 CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X),
3200 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
3201 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
3202 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
3203 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
3204 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
3205 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3206 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3207 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
3208 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
3209 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
3210 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
3211};
3212
3213
3214int __init omap2_clk_init(void)
3215{
3216 /* struct prcm_config *prcm; */
3217 struct omap_clk *c;
3218 /* u32 clkrate; */
3219 u32 cpu_clkflg;
3220
3221 if (cpu_is_omap34xx()) {
3222 cpu_mask = RATE_IN_343X;
3223 cpu_clkflg = CK_343X;
3224
3225 /*
3226 * Update this if there are further clock changes between ES2
3227 * and production parts
3228 */
3229 if (omap_rev() == OMAP3430_REV_ES1_0) {
3230 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3231 cpu_clkflg |= CK_3430ES1;
3232 } else {
3233 cpu_mask |= RATE_IN_3430ES2;
3234 cpu_clkflg |= CK_3430ES2;
3235 }
3236 }
3237
3238 clk_init(&omap2_clk_functions);
3239
3240 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
3241 clk_preinit(c->lk.clk);
3242
3243 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
3244 if (c->cpu & cpu_clkflg) {
3245 clkdev_add(&c->lk);
3246 clk_register(c->lk.clk);
3247 omap2_init_clk_clkdm(c->lk.clk);
3248 }
3249
3250 /* REVISIT: Not yet ready for OMAP3 */
3251#if 0
3252 /* Check the MPU rate set by bootloader */
3253 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
3254 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
3255 if (!(prcm->flags & cpu_mask))
3256 continue;
3257 if (prcm->xtal_speed != sys_ck.rate)
3258 continue;
3259 if (prcm->dpll_speed <= clkrate)
3260 break;
3261 }
3262 curr_prcm_set = prcm;
3263#endif
3264
3265 recalculate_root_clocks();
3266
3267 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3268 "%ld.%01ld/%ld/%ld MHz\n",
3269 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3270 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3271
3272 /*
3273 * Only enable those clocks we will need, let the drivers
3274 * enable other clocks as necessary
3275 */
3276 clk_enable_init_clocks();
3277
3278 /*
3279 * Lock DPLL5 and put it in autoidle.
3280 */
3281 if (omap_rev() >= OMAP3430_REV_ES2_0)
3282 omap3_clk_lock_dpll5();
3283
3284 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3285 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3286 arm_fck_p = clk_get(NULL, "arm_fck");
3287
3288 return 0;
3289}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 13:54:29 -0500