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authorPaul Walmsley <paul@pwsan.com>2012-09-23 19:27:43 -0400
committerPaul Walmsley <paul@pwsan.com>2012-09-23 19:27:43 -0400
commit4fb85d35bcec842e0f20437aea277157973aa45f (patch)
treed3b865af2f4066f68828806b231e4bb5b4de9ec8 /arch/arm/mach-omap2/clkt_dpll.c
parent1e2ee2a60df5c3ab74dd1c9155fb01b5bc6f807d (diff)
parenta86c0b9867940bd0ba78f109686079b4051a463d (diff)
Merge branch 'clock_devel_3.7' into hwmod_prcm_clock_a_3.7
Conflicts: arch/arm/mach-omap2/clkt34xx_dpll3m2.c arch/arm/mach-omap2/clkt_clksel.c arch/arm/mach-omap2/clock.c
Diffstat (limited to 'arch/arm/mach-omap2/clkt_dpll.c')
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 83b658bf385a..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
87 dd = clk->dpll_data; 87 dd = clk->dpll_data;
88 88
89 /* DPLL divider must result in a valid jitter correction val */ 89 /* DPLL divider must result in a valid jitter correction val */
90 fint = clk->parent->rate / n; 90 fint = __clk_get_rate(__clk_get_parent(clk)) / n;
91 91
92 if (cpu_is_omap24xx()) { 92 if (cpu_is_omap24xx()) {
93 /* Should not be called for OMAP2, so warn if it is called */ 93 /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
252 if (cpu_is_omap24xx()) { 252 if (cpu_is_omap24xx()) {
253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
254 v == OMAP2XXX_EN_DPLL_FRBYPASS) 254 v == OMAP2XXX_EN_DPLL_FRBYPASS)
255 return dd->clk_bypass->rate; 255 return __clk_get_rate(dd->clk_bypass);
256 } else if (cpu_is_omap34xx()) { 256 } else if (cpu_is_omap34xx()) {
257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
258 v == OMAP3XXX_EN_DPLL_FRBYPASS) 258 v == OMAP3XXX_EN_DPLL_FRBYPASS)
259 return dd->clk_bypass->rate; 259 return __clk_get_rate(dd->clk_bypass);
260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) { 260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
262 v == OMAP4XXX_EN_DPLL_FRBYPASS || 262 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
263 v == OMAP4XXX_EN_DPLL_MNBYPASS) 263 v == OMAP4XXX_EN_DPLL_MNBYPASS)
264 return dd->clk_bypass->rate; 264 return __clk_get_rate(dd->clk_bypass);
265 } 265 }
266 266
267 v = __raw_readl(dd->mult_div1_reg); 267 v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
270 dpll_div = v & dd->div1_mask; 270 dpll_div = v & dd->div1_mask;
271 dpll_div >>= __ffs(dd->div1_mask); 271 dpll_div >>= __ffs(dd->div1_mask);
272 272
273 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 273 dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
274 do_div(dpll_clk, dpll_div + 1); 274 do_div(dpll_clk, dpll_div + 1);
275 275
276 return dpll_clk; 276 return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
296 unsigned long scaled_rt_rp; 296 unsigned long scaled_rt_rp;
297 unsigned long new_rate = 0; 297 unsigned long new_rate = 0;
298 struct dpll_data *dd; 298 struct dpll_data *dd;
299 unsigned long ref_rate;
300 const char *clk_name;
299 301
300 if (!clk || !clk->dpll_data) 302 if (!clk || !clk->dpll_data)
301 return ~0; 303 return ~0;
302 304
303 dd = clk->dpll_data; 305 dd = clk->dpll_data;
304 306
307 ref_rate = __clk_get_rate(dd->clk_ref);
308 clk_name = __clk_get_name(clk);
305 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", 309 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
306 clk->name, target_rate); 310 clk_name, target_rate);
307 311
308 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 312 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
309 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 313 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
310 314
311 dd->last_rounded_rate = 0; 315 dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
332 break; 336 break;
333 337
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 338 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
335 dd->clk_ref->rate); 339 ref_rate);
336 340
337 /* m can't be set low enough for this n - try with a larger n */ 341 /* m can't be set low enough for this n - try with a larger n */
338 if (r == DPLL_MULT_UNDERFLOW) 342 if (r == DPLL_MULT_UNDERFLOW)
339 continue; 343 continue;
340 344
341 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", 345 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
342 clk->name, m, n, new_rate); 346 clk_name, m, n, new_rate);
343 347
344 if (target_rate == new_rate) { 348 if (target_rate == new_rate) {
345 dd->last_rounded_m = m; 349 dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
350 } 354 }
351 355
352 if (target_rate != new_rate) { 356 if (target_rate != new_rate) {
353 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, 357 pr_debug("clock: %s: cannot round to rate %ld\n",
354 target_rate); 358 clk_name, target_rate);
355 return ~0; 359 return ~0;
356 } 360 }
357 361