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authorRajendra Nayak <rnayak@ti.com>2012-04-27 06:29:32 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:10:18 -0500
commited1ebc4948fdfe4c68865e5543b4a68e5a55973b (patch)
tree6d781e2833bdd91472f3a86e38eb4a8ae4e2b379 /arch/arm/mach-omap2/clkt2xxx_dpllcore.c
parentb4777a21381fd1f87be8c606a616b7f97f485d2b (diff)
ARM: OMAP2: clock: Convert to common clk
Convert all OMAP2 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c')
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index e687163a68fe..9d8388b7ee97 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -41,7 +41,11 @@
41 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set 41 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
42 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). 42 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
43 */ 43 */
44#ifdef CONFIG_COMMON_CLK
45static struct clk_hw_omap *dpll_core_ck;
46#else
44static struct clk *dpll_core_ck; 47static struct clk *dpll_core_ck;
48#endif
45 49
46/** 50/**
47 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 51 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
@@ -105,13 +109,25 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
105 109
106} 110}
107 111
112#ifdef CONFIG_COMMON_CLK
113unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
114 unsigned long parent_rate)
115#else
108unsigned long omap2_dpllcore_recalc(struct clk *clk) 116unsigned long omap2_dpllcore_recalc(struct clk *clk)
117#endif
109{ 118{
110 return omap2xxx_clk_get_core_rate(); 119 return omap2xxx_clk_get_core_rate();
111} 120}
112 121
122#ifdef CONFIG_COMMON_CLK
123int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
124 unsigned long parent_rate)
125{
126 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
127#else
113int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 128int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
114{ 129{
130#endif
115 u32 cur_rate, low, mult, div, valid_rate, done_rate; 131 u32 cur_rate, low, mult, div, valid_rate, done_rate;
116 u32 bypass = 0; 132 u32 bypass = 0;
117 struct prcm_config tmpset; 133 struct prcm_config tmpset;
@@ -189,8 +205,16 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
189 * statically defined, this code may need to change to increment some 205 * statically defined, this code may need to change to increment some
190 * kind of use count on dpll_ck. 206 * kind of use count on dpll_ck.
191 */ 207 */
208#ifdef CONFIG_COMMON_CLK
209void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
210#else
192void omap2xxx_clkt_dpllcore_init(struct clk *clk) 211void omap2xxx_clkt_dpllcore_init(struct clk *clk)
212#endif
193{ 213{
194 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); 214 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
215#ifdef CONFIG_COMMON_CLK
216 dpll_core_ck = to_clk_hw_omap(hw);
217#else
195 dpll_core_ck = clk; 218 dpll_core_ck = clk;
219#endif
196} 220}