ARM: mmp: add usb device support for PXA910

Add usb device support for Marvell PXA910.
Actually PXA920 will use the same device.

Signed-off-by: Neil Zhang <zhangwm@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>

6 files changed, 549 insertions, 1 deletions

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a3ab6e..fa03974fd838 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -113,4 +113,11 @@ config CPU_MMP2
         select CPU_PJ4
         help
           Select code specific to MMP2. MMP2 is ARMv7 compatible.
+
+config USB_EHCI_MV_U2O
+        bool "EHCI support for PXA USB OTG controller"
+        depends on USB_EHCI_MV
+        help
+          Enables support for OTG controller which can be switched to host mode.
+
 endif
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index 191d9dea8731..262179f45109 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -9,9 +9,13 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/delay.h>
 
 #include <asm/irq.h>
+#include <mach/irqs.h>
 #include <mach/devices.h>
+#include <mach/cputype.h>
+#include <mach/regs-usb.h>
 
 int __init pxa_register_device(struct pxa_device_desc *desc,
                                 void *data, size_t size)
@@ -67,3 +71,281 @@ int __init pxa_register_device(struct pxa_device_desc *desc,
 
         return platform_device_add(pdev);
 }
+
+#if defined(CONFIG_USB) || defined(CONFIG_USB_GADGET)
+
+/*****************************************************************************
+ * The registers read/write routines
+ *****************************************************************************/
+
+static unsigned int u2o_get(void __iomem *base, unsigned int offset)
+{
+        return readl_relaxed(base + offset);
+}
+
+static void u2o_set(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        u32 reg;
+
+        reg = readl_relaxed(base + offset);
+        reg |= value;
+        writel_relaxed(reg, base + offset);
+        readl_relaxed(base + offset);
+}
+
+static void u2o_clear(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        u32 reg;
+
+        reg = readl_relaxed(base + offset);
+        reg &= ~value;
+        writel_relaxed(reg, base + offset);
+        readl_relaxed(base + offset);
+}
+
+static void u2o_write(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        writel_relaxed(value, base + offset);
+        readl_relaxed(base + offset);
+}
+
+#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV)
+
+#if defined(CONFIG_CPU_PXA910)
+
+static DEFINE_MUTEX(phy_lock);
+static int phy_init_cnt;
+
+static int usb_phy_init_internal(void __iomem *base)
+{
+        int loops;
+
+        pr_info("Init usb phy!!!\n");
+
+        /* Initialize the USB PHY power */
+        if (cpu_is_pxa910()) {
+                u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
+                        | (1<<UTMI_CTRL_PU_REF_SHIFT));
+        }
+
+        u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
+        u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
+
+        /* UTMI_PLL settings */
+        u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
+                | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
+                | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
+                | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
+
+        u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
+                | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
+                | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
+                | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
+
+        /* UTMI_TX */
+        u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
+                | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
+                | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
+                | UTMI_TX_AMP_MASK);
+        u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
+                | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
+                | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
+
+        /* UTMI_RX */
+        u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
+                | UTMI_REG_SQ_LENGTH_MASK);
+        u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
+                | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
+
+        /* UTMI_IVREF */
+        if (cpu_is_pxa168())
+                /* fixing Microsoft Altair board interface with NEC hub issue -
+                 * Set UTMI_IVREF from 0x4a3 to 0x4bf */
+                u2o_write(base, UTMI_IVREF, 0x4bf);
+
+        /* toggle VCOCAL_START bit of UTMI_PLL */
+        udelay(200);
+        u2o_set(base, UTMI_PLL, VCOCAL_START);
+        udelay(40);
+        u2o_clear(base, UTMI_PLL, VCOCAL_START);
+
+        /* toggle REG_RCAL_START bit of UTMI_TX */
+        udelay(400);
+        u2o_set(base, UTMI_TX, REG_RCAL_START);
+        udelay(40);
+        u2o_clear(base, UTMI_TX, REG_RCAL_START);
+        udelay(400);
+
+        /* Make sure PHY PLL is ready */
+        loops = 0;
+        while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
+                mdelay(1);
+                loops++;
+                if (loops > 100) {
+                        printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
+                                u2o_get(base, UTMI_PLL));
+                        break;
+                }
+        }
+
+        if (cpu_is_pxa168()) {
+                u2o_set(base, UTMI_RESERVE, 1 << 5);
+                /* Turn on UTMI PHY OTG extension */
+                u2o_write(base, UTMI_OTG_ADDON, 1);
+        }
+
+        return 0;
+}
+
+static int usb_phy_deinit_internal(void __iomem *base)
+{
+        pr_info("Deinit usb phy!!!\n");
+
+        if (cpu_is_pxa168())
+                u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
+
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
+        u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
+        u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
+
+        return 0;
+}
+
+int pxa_usb_phy_init(void __iomem *phy_reg)
+{
+        mutex_lock(&phy_lock);
+        if (phy_init_cnt++ == 0)
+                usb_phy_init_internal(phy_reg);
+        mutex_unlock(&phy_lock);
+        return 0;
+}
+
+void pxa_usb_phy_deinit(void __iomem *phy_reg)
+{
+        WARN_ON(phy_init_cnt == 0);
+
+        mutex_lock(&phy_lock);
+        if (--phy_init_cnt == 0)
+                usb_phy_deinit_internal(phy_reg);
+        mutex_unlock(&phy_lock);
+}
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_USB_SUPPORT
+static u64 usb_dma_mask = ~(u32)0;
+
+#ifdef CONFIG_USB_MV_UDC
+struct resource pxa168_u2o_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa168_device_u2o = {
+        .name           = "mv-udc",
+        .id             = -1,
+        .resource       = pxa168_u2o_resources,
+        .num_resources  = ARRAY_SIZE(pxa168_u2o_resources),
+        .dev            =  {
+                .dma_mask       = &usb_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        }
+};
+#endif /* CONFIG_USB_MV_UDC */
+
+#ifdef CONFIG_USB_EHCI_MV_U2O
+struct resource pxa168_u2oehci_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa168_device_u2oehci = {
+        .name           = "pxa-u2oehci",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &usb_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+
+        .num_resources  = ARRAY_SIZE(pxa168_u2oehci_resources),
+        .resource       = pxa168_u2oehci_resources,
+};
+#endif
+
+#if defined(CONFIG_USB_MV_OTG)
+struct resource pxa168_u2ootg_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa168_device_u2ootg = {
+        .name           = "mv-otg",
+        .id             = -1,
+        .dev  = {
+                .dma_mask          = &usb_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+
+        .num_resources  = ARRAY_SIZE(pxa168_u2ootg_resources),
+        .resource      = pxa168_u2ootg_resources,
+};
+#endif /* CONFIG_USB_MV_OTG */
+
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
index d0ec7dae88e4..21217ef11b64 100644
--- a/arch/arm/mach-mmp/include/mach/devices.h
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -50,4 +50,7 @@ struct pxa_device_desc mmp2_device_##_name __initdata = {		\
 }
 
 extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
+extern int pxa_usb_phy_init(void __iomem *phy_reg);
+extern void pxa_usb_phy_deinit(void __iomem *phy_reg);
+
 #endif /* __MACH_DEVICE_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index e2e1f1e5e124..793634c837ef 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -20,6 +20,9 @@ extern struct pxa_device_desc pxa910_device_pwm2;
 extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
+extern struct platform_device pxa168_device_u2o;
+extern struct platform_device pxa168_device_u2ootg;
+extern struct platform_device pxa168_device_u2oehci;
 
 extern struct platform_device pxa910_device_gpio;
 extern struct platform_device pxa910_device_rtc;
diff --git a/arch/arm/mach-mmp/include/mach/regs-usb.h b/arch/arm/mach-mmp/include/mach/regs-usb.h
new file mode 100644
index 000000000000..b047bf487506
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-usb.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_REGS_USB_H
+#define __ASM_ARCH_REGS_USB_H
+
+#define PXA168_U2O_REGBASE      (0xd4208000)
+#define PXA168_U2O_PHYBASE      (0xd4207000)
+
+#define PXA168_U2H_REGBASE      (0xd4209000)
+#define PXA168_U2H_PHYBASE      (0xd4206000)
+
+#define MMP3_HSIC1_REGBASE      (0xf0001000)
+#define MMP3_HSIC1_PHYBASE      (0xf0001800)
+
+#define MMP3_HSIC2_REGBASE      (0xf0002000)
+#define MMP3_HSIC2_PHYBASE      (0xf0002800)
+
+#define MMP3_FSIC_REGBASE       (0xf0003000)
+#define MMP3_FSIC_PHYBASE       (0xf0003800)
+
+
+#define USB_REG_RANGE           (0x1ff)
+#define USB_PHY_RANGE           (0xff)
+
+/* registers */
+#define U2x_CAPREGS_OFFSET       0x100
+
+/* phy regs */
+#define UTMI_REVISION           0x0
+#define UTMI_CTRL               0x4
+#define UTMI_PLL                0x8
+#define UTMI_TX                 0xc
+#define UTMI_RX                 0x10
+#define UTMI_IVREF              0x14
+#define UTMI_T0                 0x18
+#define UTMI_T1                 0x1c
+#define UTMI_T2                 0x20
+#define UTMI_T3                 0x24
+#define UTMI_T4                 0x28
+#define UTMI_T5                 0x2c
+#define UTMI_RESERVE            0x30
+#define UTMI_USB_INT            0x34
+#define UTMI_DBG_CTL            0x38
+#define UTMI_OTG_ADDON          0x3c
+
+/* For UTMICTRL Register */
+#define UTMI_CTRL_USB_CLK_EN                    (1 << 31)
+/* pxa168 */
+#define UTMI_CTRL_SUSPEND_SET1                  (1 << 30)
+#define UTMI_CTRL_SUSPEND_SET2                  (1 << 29)
+#define UTMI_CTRL_RXBUF_PDWN                    (1 << 24)
+#define UTMI_CTRL_TXBUF_PDWN                    (1 << 11)
+
+#define UTMI_CTRL_INPKT_DELAY_SHIFT             30
+#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT         28
+#define UTMI_CTRL_PU_REF_SHIFT                  20
+#define UTMI_CTRL_ARC_PULLDN_SHIFT              12
+#define UTMI_CTRL_PLL_PWR_UP_SHIFT              1
+#define UTMI_CTRL_PWR_UP_SHIFT                  0
+
+/* For UTMI_PLL Register */
+#define UTMI_PLL_PLLCALI12_SHIFT                29
+#define UTMI_PLL_PLLCALI12_MASK                 (0x3 << 29)
+
+#define UTMI_PLL_PLLVDD18_SHIFT                 27
+#define UTMI_PLL_PLLVDD18_MASK                  (0x3 << 27)
+
+#define UTMI_PLL_PLLVDD12_SHIFT                 25
+#define UTMI_PLL_PLLVDD12_MASK                  (0x3 << 25)
+
+#define UTMI_PLL_CLK_BLK_EN_SHIFT               24
+#define CLK_BLK_EN                              (0x1 << 24)
+#define PLL_READY                               (0x1 << 23)
+#define KVCO_EXT                                (0x1 << 22)
+#define VCOCAL_START                            (0x1 << 21)
+
+#define UTMI_PLL_KVCO_SHIFT                     15
+#define UTMI_PLL_KVCO_MASK                      (0x7 << 15)
+
+#define UTMI_PLL_ICP_SHIFT                      12
+#define UTMI_PLL_ICP_MASK                       (0x7 << 12)
+
+#define UTMI_PLL_FBDIV_SHIFT                    4
+#define UTMI_PLL_FBDIV_MASK                     (0xFF << 4)
+
+#define UTMI_PLL_REFDIV_SHIFT                   0
+#define UTMI_PLL_REFDIV_MASK                    (0xF << 0)
+
+/* For UTMI_TX Register */
+#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT           27
+#define UTMI_TX_REG_EXT_FS_RCAL_MASK            (0xf << 27)
+
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT        26
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK         (0x1 << 26)
+
+#define UTMI_TX_TXVDD12_SHIFT                   22
+#define UTMI_TX_TXVDD12_MASK                    (0x3 << 22)
+
+#define UTMI_TX_CK60_PHSEL_SHIFT                17
+#define UTMI_TX_CK60_PHSEL_MASK                 (0xf << 17)
+
+#define UTMI_TX_IMPCAL_VTH_SHIFT                14
+#define UTMI_TX_IMPCAL_VTH_MASK                 (0x7 << 14)
+
+#define REG_RCAL_START                          (0x1 << 12)
+
+#define UTMI_TX_LOW_VDD_EN_SHIFT                11
+
+#define UTMI_TX_AMP_SHIFT                       0
+#define UTMI_TX_AMP_MASK                        (0x7 << 0)
+
+/* For UTMI_RX Register */
+#define UTMI_REG_SQ_LENGTH_SHIFT                15
+#define UTMI_REG_SQ_LENGTH_MASK                 (0x3 << 15)
+
+#define UTMI_RX_SQ_THRESH_SHIFT                 4
+#define UTMI_RX_SQ_THRESH_MASK                  (0xf << 4)
+
+#define UTMI_OTG_ADDON_OTG_ON                   (1 << 0)
+
+/* For MMP3 USB Phy */
+#define USB2_PLL_REG0           0x4
+#define USB2_PLL_REG1           0x8
+#define USB2_TX_REG0            0x10
+#define USB2_TX_REG1            0x14
+#define USB2_TX_REG2            0x18
+#define USB2_RX_REG0            0x20
+#define USB2_RX_REG1            0x24
+#define USB2_RX_REG2            0x28
+#define USB2_ANA_REG0           0x30
+#define USB2_ANA_REG1           0x34
+#define USB2_ANA_REG2           0x38
+#define USB2_DIG_REG0           0x3C
+#define USB2_DIG_REG1           0x40
+#define USB2_DIG_REG2           0x44
+#define USB2_DIG_REG3           0x48
+#define USB2_TEST_REG0          0x4C
+#define USB2_TEST_REG1          0x50
+#define USB2_TEST_REG2          0x54
+#define USB2_CHARGER_REG0       0x58
+#define USB2_OTG_REG0           0x5C
+#define USB2_PHY_MON0           0x60
+#define USB2_RESETVE_REG0       0x64
+#define USB2_ICID_REG0          0x78
+#define USB2_ICID_REG1          0x7C
+
+/* USB2_PLL_REG0 */
+/* This is for Ax stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3               0
+#define USB2_PLL_FBDIV_MASK_MMP3                (0xFF << 0)
+
+#define USB2_PLL_REFDIV_SHIFT_MMP3              8
+#define USB2_PLL_REFDIV_MASK_MMP3               (0xF << 8)
+
+#define USB2_PLL_VDD12_SHIFT_MMP3               12
+#define USB2_PLL_VDD18_SHIFT_MMP3               14
+
+/* This is for B0 stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3_B0            0
+#define USB2_PLL_REFDIV_SHIFT_MMP3_B0           9
+#define USB2_PLL_VDD18_SHIFT_MMP3_B0            14
+#define USB2_PLL_FBDIV_MASK_MMP3_B0             0x01FF
+#define USB2_PLL_REFDIV_MASK_MMP3_B0            0x3E00
+
+#define USB2_PLL_CAL12_SHIFT_MMP3               0
+#define USB2_PLL_CALI12_MASK_MMP3               (0x3 << 0)
+
+#define USB2_PLL_VCOCAL_START_SHIFT_MMP3        2
+
+#define USB2_PLL_KVCO_SHIFT_MMP3                4
+#define USB2_PLL_KVCO_MASK_MMP3                 (0x7<<4)
+
+#define USB2_PLL_ICP_SHIFT_MMP3                 8
+#define USB2_PLL_ICP_MASK_MMP3                  (0x7<<8)
+
+#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3         12
+
+#define USB2_PLL_PU_PLL_SHIFT_MMP3              13
+#define USB2_PLL_PU_PLL_MASK                    (0x1 << 13)
+
+#define USB2_PLL_READY_MASK_MMP3                (0x1 << 15)
+
+/* USB2_TX_REG0 */
+#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3           8
+#define USB2_TX_IMPCAL_VTH_MASK_MMP3            (0x7 << 8)
+
+#define USB2_TX_RCAL_START_SHIFT_MMP3           13
+
+/* USB2_TX_REG1 */
+#define USB2_TX_CK60_PHSEL_SHIFT_MMP3           0
+#define USB2_TX_CK60_PHSEL_MASK_MMP3            (0xf << 0)
+
+#define USB2_TX_AMP_SHIFT_MMP3                  4
+#define USB2_TX_AMP_MASK_MMP3                   (0x7 << 4)
+
+#define USB2_TX_VDD12_SHIFT_MMP3                8
+#define USB2_TX_VDD12_MASK_MMP3                 (0x3 << 8)
+
+/* USB2_TX_REG2 */
+#define USB2_TX_DRV_SLEWRATE_SHIFT              10
+
+/* USB2_RX_REG0 */
+#define USB2_RX_SQ_THRESH_SHIFT_MMP3            4
+#define USB2_RX_SQ_THRESH_MASK_MMP3             (0xf << 4)
+
+#define USB2_RX_SQ_LENGTH_SHIFT_MMP3            10
+#define USB2_RX_SQ_LENGTH_MASK_MMP3             (0x3 << 10)
+
+/* USB2_ANA_REG1*/
+#define USB2_ANA_PU_ANA_SHIFT_MMP3              14
+
+/* USB2_OTG_REG0 */
+#define USB2_OTG_PU_OTG_SHIFT_MMP3              3
+
+/* fsic registers */
+#define FSIC_MISC                       0x4
+#define FSIC_INT                        0x28
+#define FSIC_CTRL                       0x30
+
+/* HSIC registers */
+#define HSIC_PAD_CTRL                   0x4
+
+#define HSIC_CTRL                       0x8
+#define HSIC_CTRL_HSIC_ENABLE           (1<<7)
+#define HSIC_CTRL_PLL_BYPASS            (1<<4)
+
+#define TEST_GRP_0                      0xc
+#define TEST_GRP_1                      0x10
+
+#define HSIC_INT                        0x14
+#define HSIC_INT_READY_INT_EN           (1<<10)
+#define HSIC_INT_CONNECT_INT_EN         (1<<9)
+#define HSIC_INT_CORE_INT_EN            (1<<8)
+#define HSIC_INT_HS_READY               (1<<2)
+#define HSIC_INT_CONNECT                (1<<1)
+#define HSIC_INT_CORE                   (1<<0)
+
+#define HSIC_CONFIG                     0x18
+#define USBHSIC_CTRL                    0x20
+
+#define HSIC_USB_CTRL                   0x28
+#define HSIC_USB_CTRL_CLKEN             1
+#define HSIC_USB_CLK_PHY                0x0
+#define HSIC_USB_CLK_PMU                0x1
+
+#endif /* __ASM_ARCH_PXA_U2O_H */
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 43f8bcc29b67..6da52e9f2bdc 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -109,7 +109,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
+        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
         INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };