diff options
author | Krzysztof Hałasa <khc@pm.waw.pl> | 2009-11-17 12:48:23 -0500 |
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committer | Krzysztof Hałasa <khc@pm.waw.pl> | 2009-12-05 10:58:41 -0500 |
commit | 8d3fdf31dd2066533861bb57ed7df1ae1b1f5fcc (patch) | |
tree | 5186d63c67dee5454348e55cf46d31053672d67d /arch/arm/mach-ixp4xx/nas100d-pci.c | |
parent | a8b7b34075f693632cd1483b817d4211c7a63257 (diff) |
IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx/nas100d-pci.c')
-rw-r--r-- | arch/arm/mach-ixp4xx/nas100d-pci.c | 50 |
1 files changed, 20 insertions, 30 deletions
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index ac04fc1a6c34..d0cea34cf61e 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c | |||
@@ -21,49 +21,39 @@ | |||
21 | #include <asm/mach/pci.h> | 21 | #include <asm/mach/pci.h> |
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | 23 | ||
24 | #define NAS100D_PCI_MAX_DEV 3 | 24 | #define MAX_DEV 3 |
25 | #define NAS100D_PCI_IRQ_LINES 3 | 25 | #define IRQ_LINES 3 |
26 | 26 | ||
27 | /* PCI controller GPIO to IRQ pin mappings */ | 27 | /* PCI controller GPIO to IRQ pin mappings */ |
28 | #define NAS100D_PCI_INTA_PIN 11 | 28 | #define INTA 11 |
29 | #define NAS100D_PCI_INTB_PIN 10 | 29 | #define INTB 10 |
30 | #define NAS100D_PCI_INTC_PIN 9 | 30 | #define INTC 9 |
31 | #define NAS100D_PCI_INTD_PIN 8 | 31 | #define INTD 8 |
32 | #define NAS100D_PCI_INTE_PIN 7 | 32 | #define INTE 7 |
33 | |||
34 | #define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
35 | #define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
36 | #define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
37 | #define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
38 | #define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 | ||
39 | 33 | ||
40 | void __init nas100d_pci_preinit(void) | 34 | void __init nas100d_pci_preinit(void) |
41 | { | 35 | { |
42 | set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); | 36 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
43 | set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | 37 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
44 | set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 38 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
45 | set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 39 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
46 | set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | 40 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
47 | |||
48 | ixp4xx_pci_preinit(); | 41 | ixp4xx_pci_preinit(); |
49 | } | 42 | } |
50 | 43 | ||
51 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 44 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
52 | { | 45 | { |
53 | static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = | 46 | static int pci_irq_table[MAX_DEV][IRQ_LINES] = { |
54 | { | 47 | { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, |
55 | { IRQ_NAS100D_PCI_INTA, -1, -1 }, | 48 | { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, |
56 | { IRQ_NAS100D_PCI_INTB, -1, -1 }, | 49 | { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), |
57 | { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, | 50 | IXP4XX_GPIO_IRQ(INTE) }, |
58 | }; | 51 | }; |
59 | 52 | ||
60 | int irq = -1; | 53 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
61 | 54 | return pci_irq_table[slot - 1][pin - 1]; | |
62 | if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && | ||
63 | pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) | ||
64 | irq = pci_irq_table[slot-1][pin-1]; | ||
65 | 55 | ||
66 | return irq; | 56 | return -1; |
67 | } | 57 | } |
68 | 58 | ||
69 | struct hw_pci __initdata nas100d_pci = { | 59 | struct hw_pci __initdata nas100d_pci = { |