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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-01-17 14:27:09 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-02 04:35:35 -0400
commite606a940cba4083b9c382c17251636856e03346b (patch)
treeccdc15e24c51eee2ae61f12ecd40e85a3ccea26f /arch/arm/mach-integrator/include/mach
parent4ce1755275c13eb0de90fe23c950bce5e81e680f (diff)
ARM: Realview/Versatile/Integrator: remove unused definitions from platform.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-integrator/include/mach')
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h42
1 files changed, 2 insertions, 40 deletions
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index 0e172e48bc85..5e6ea5cfea6e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -23,9 +23,6 @@
23 * 23 *
24 * Integrator address map 24 * Integrator address map
25 * 25 *
26 * NOTE: This is a multi-hosted header file for use with uHAL and
27 * supported debuggers.
28 *
29 * ***********************************************************************/ 26 * ***********************************************************************/
30 27
31#ifndef __address_h 28#ifndef __address_h
@@ -330,20 +327,6 @@
330 */ 327 */
331#define PHYS_PCI_V3_BASE 0x62000000 328#define PHYS_PCI_V3_BASE 0x62000000
332 329
333#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
334
335/* 'export' these to UHAL */
336#define UHAL_PCI_IO PCI_IO_BASE
337#define UHAL_PCI_MEM PCI_MEM_BASE
338#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
339#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
340#define UHAL_PCI_MAX_SLOT 20
341
342/* ========================================================================
343 * Start of uHAL definitions
344 * ========================================================================
345 */
346
347/* ------------------------------------------------------------------------ 330/* ------------------------------------------------------------------------
348 * Integrator Interrupt Controllers 331 * Integrator Interrupt Controllers
349 * ------------------------------------------------------------------------ 332 * ------------------------------------------------------------------------
@@ -391,7 +374,7 @@
391 */ 374 */
392 375
393/* ------------------------------------------------------------------------ 376/* ------------------------------------------------------------------------
394 * LED's - The header LED is not accessible via the uHAL API 377 * LED's
395 * ------------------------------------------------------------------------ 378 * ------------------------------------------------------------------------
396 * 379 *
397 */ 380 */
@@ -404,34 +387,18 @@
404#define LED_BANK INTEGRATOR_DBG_LEDS 387#define LED_BANK INTEGRATOR_DBG_LEDS
405 388
406/* 389/*
407 * Memory definitions - run uHAL out of SSRAM.
408 *
409 */
410#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
411
412/*
413 * Clean base - dummy
414 *
415 */
416#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
417
418/*
419 * Timer definitions 390 * Timer definitions
420 * 391 *
421 * Only use timer 1 & 2 392 * Only use timer 1 & 2
422 * (both run at 24MHz and will need the clock divider set to 16). 393 * (both run at 24MHz and will need the clock divider set to 16).
423 * 394 *
424 * Timer 0 runs at bus frequency and therefore could vary and currently 395 * Timer 0 runs at bus frequency
425 * uHAL can't handle that.
426 *
427 */ 396 */
428 397
429#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 398#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
430#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 399#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
431#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 400#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
432 401
433#define MAX_TIMER 2
434#define MAX_PERIOD 699050
435#define TICKS_PER_uSEC 24 402#define TICKS_PER_uSEC 24
436 403
437/* 404/*
@@ -439,14 +406,9 @@
439 * 406 *
440 */ 407 */
441#define mSEC_1 1000 408#define mSEC_1 1000
442#define mSEC_5 (mSEC_1 * 5)
443#define mSEC_10 (mSEC_1 * 10) 409#define mSEC_10 (mSEC_1 * 10)
444#define mSEC_25 (mSEC_1 * 25)
445#define SEC_1 (mSEC_1 * 1000)
446 410
447#define INTEGRATOR_CSR_BASE 0x10000000 411#define INTEGRATOR_CSR_BASE 0x10000000
448#define INTEGRATOR_CSR_SIZE 0x10000000 412#define INTEGRATOR_CSR_SIZE 0x10000000
449 413
450#endif 414#endif
451
452/* END */