diff options
| author | Peter Chen <peter.chen@freescale.com> | 2014-02-27 20:04:01 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:48 -0400 |
| commit | b8ce877a03bace6c07e155ad59220fb62bb5a83f (patch) | |
| tree | 929d5223f8f88804df874b9496d113ab3caad6f9 /arch/arm/mach-imx | |
| parent | dbd5d51fe88bc3903c6018c7f1c13aef9269d782 (diff) | |
ENGR00301290-2 ARM: imx6sx: enable usbphy dummy clock
If usbphy is enabled, we need to enable usbphy dump clock, it is
the requirement from IC engineer, it is used to guarantee some
RTL operation correctness without software operation.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 1bc072c0d799..02b227241166 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c | |||
| @@ -431,6 +431,11 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 431 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 431 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 432 | clk_prepare_enable(clks[clks_init_on[i]]); | 432 | clk_prepare_enable(clks[clks_init_on[i]]); |
| 433 | 433 | ||
| 434 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { | ||
| 435 | clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]); | ||
| 436 | clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); | ||
| 437 | } | ||
| 438 | |||
| 434 | /* set parent clock for LCDIF1 pixel clock */ | 439 | /* set parent clock for LCDIF1 pixel clock */ |
| 435 | clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); | 440 | clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); |
| 436 | clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); | 441 | clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); |