diff options
| author | Fugang Duan <B38611@freescale.com> | 2014-02-14 22:36:36 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:31 -0400 |
| commit | 8452fe0f4eea62b3172726974c91006ae1d02a5e (patch) | |
| tree | 2b116927ba898ff146a00baadd117306f0c08cfa /arch/arm/mach-imx | |
| parent | a5720c7e5a26f06597bfeb767ba52e93abd37c4b (diff) | |
ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk support
Add i.mx6sx enet clk support:
- Add enet2 refrence clock.
- Add PTP clock.
- Set enet system AHB clock to 200Mh.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 757dbdbd4ec1..cb8b1a7e2cab 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2014 Freescale Semiconductor, Inc. |
| 3 | * | 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 5 | * License. You may obtain a copy of the GNU General Public License |
| @@ -159,6 +159,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 159 | clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, | 159 | clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, |
| 160 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | 160 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
| 161 | &imx_ccm_lock); | 161 | &imx_ccm_lock); |
| 162 | clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, | ||
| 163 | base + 0xe0, 2, 2, 0, clk_enet_ref_table, | ||
| 164 | &imx_ccm_lock); | ||
| 165 | clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); | ||
| 166 | |||
| 167 | clks[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); | ||
| 168 | clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21); | ||
| 162 | 169 | ||
| 163 | /* name parent_name reg idx */ | 170 | /* name parent_name reg idx */ |
| 164 | clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | 171 | clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
| @@ -423,6 +430,22 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 423 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 430 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 424 | clk_prepare_enable(clks[clks_init_on[i]]); | 431 | clk_prepare_enable(clks[clks_init_on[i]]); |
| 425 | 432 | ||
| 433 | /* | ||
| 434 | * Init enet system AHB clock, set to 200Mhz | ||
| 435 | * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB | ||
| 436 | */ | ||
| 437 | clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); | ||
| 438 | clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]); | ||
| 439 | clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000); | ||
| 440 | clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000); | ||
| 441 | clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); | ||
| 442 | |||
| 443 | /* | ||
| 444 | * Need to keep the ENET clocks enabled, else the system | ||
| 445 | * hangs when ENET clocks are disabled in the driver. | ||
| 446 | */ | ||
| 447 | clk_prepare_enable(clks[IMX6SX_CLK_ENET]); | ||
| 448 | |||
| 426 | /* Set initial power mode */ | 449 | /* Set initial power mode */ |
| 427 | imx6_set_lpm(WAIT_CLOCKED); | 450 | imx6_set_lpm(WAIT_CLOCKED); |
| 428 | 451 | ||