diff options
author | Jaecheol Lee <jc.lee@samsung.com> | 2012-02-01 22:31:01 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-11 01:30:27 -0500 |
commit | d074de8ef5a8b241c129690014138fcadcd72bc4 (patch) | |
tree | 9ea95f87e3f4cc63acb71dd18fe1ac29759da22b /arch/arm/mach-exynos/include/mach/regs-clock.h | |
parent | a2b9676db08b3be717af16e333396a97eeee1745 (diff) |
ARM: EXYNOS: add clock registers for exynos4x12-cpufreq
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-clock.h')
-rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 790f525d1557..b1a2aeb256fe 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h | |||
@@ -160,6 +160,15 @@ | |||
160 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) | 160 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
161 | #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) | 161 | #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) |
162 | #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) | 162 | #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
163 | #define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 | ||
164 | #define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) | ||
165 | |||
166 | #define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 | ||
167 | #define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) | ||
168 | #define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 | ||
169 | #define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) | ||
170 | #define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 | ||
171 | #define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) | ||
163 | 172 | ||
164 | #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) | 173 | #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) |
165 | #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | 174 | #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |