ARM: EXYNOS: Change System MMU platform device definitions

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 38 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 024d38ff1718..69f2ea6fb0d2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -91,6 +91,7 @@
 #define EXYNOS4_PA_PDMA1                0x12690000
 
 #define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
+#define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
 #define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
@@ -99,6 +100,12 @@
 #define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
 #define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
 #define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
+#define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
+#define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
+#define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
 #define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
 #define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
 #define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
@@ -106,6 +113,37 @@
 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D            0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP           0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS           0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP           0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC           0x12370000
+#define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
+#define EXYNOS5_PA_SYSMMU_FD            0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
+#define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
+#define EXYNOS5_PA_SYSMMU_TV            0x14650000
+
 #define EXYNOS4_PA_SPI0                 0x13920000
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000