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authorKukjin Kim <kgene.kim@samsung.com>2012-05-12 02:31:37 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-05-12 02:31:37 -0400
commitad28536a898fbdc8c57d64348e310e1bda776963 (patch)
treeb057f2d095797399ce6ef01312359712e4b67b15 /arch/arm/mach-exynos/include/mach/map.h
parent18c411b7974f47f84c29507bdf3e0573890c0f0e (diff)
parent2a96536e77b43cf1e70ab3ad8b46b98ab52b56c1 (diff)
Merge branch 'next/devel-samsung-iommu' into next/devel-samsung
Conflicts: arch/arm/mach-exynos/Makefile
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/map.h')
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 6e6d11ff352a..0e2292d04550 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -95,6 +95,7 @@
95#define EXYNOS5_PA_PDMA1 0x121B0000 95#define EXYNOS5_PA_PDMA1 0x121B0000
96 96
97#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 97#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
98#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
98#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 99#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
99#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 100#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
100#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 101#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
@@ -103,6 +104,12 @@
103#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 104#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
104#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 105#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
105#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 106#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
107#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
108#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
109#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
110#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
111#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
112#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
106#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 113#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
107#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 114#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
108#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 115#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
@@ -110,6 +117,37 @@
110#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 117#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
111#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 118#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
112#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 119#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
120
121#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
122#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
123#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
124#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
125#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
126#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
127#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
128#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
129#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
130#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
131#define EXYNOS5_PA_SYSMMU_GPS 0x12630000
132#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
133#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
134#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
135#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
136#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
137#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
138#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
139#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
140#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
141#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
142#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
143#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
144#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
145#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
146#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
147#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
148#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
149#define EXYNOS5_PA_SYSMMU_TV 0x14650000
150
113#define EXYNOS4_PA_SPI0 0x13920000 151#define EXYNOS4_PA_SPI0 0x13920000
114#define EXYNOS4_PA_SPI1 0x13930000 152#define EXYNOS4_PA_SPI1 0x13930000
115#define EXYNOS4_PA_SPI2 0x13940000 153#define EXYNOS4_PA_SPI2 0x13940000