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authorOlof Johansson <olof@lixom.net>2012-09-22 17:09:21 -0400
committerOlof Johansson <olof@lixom.net>2012-09-22 17:22:47 -0400
commit0d601f613b8557cf6489f06251ae5dc383b811d0 (patch)
tree05f3a4d054e0bddc308af479918ce67cd02e8eba /arch/arm/mach-dove
parentd7ffa2234c186ce040e79b43639628c1c482b115 (diff)
parent5b40baee4a39d96d4d6a48a2b2383982912c429b (diff)
Merge branch 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux into late/kirkwood
* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: add address decoding controller to the DT arm: mvebu: add basic address decoding support to Armada 370/XP arm: plat-orion: make bridge_virt_base non-const to support DT use case arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option arm: plat-orion: use void __iomem pointers for addr-map functions arm: plat-orion: use void __iomem pointers for time functions arm: plat-orion: use void __iomem pointers for MPP functions arm: plat-orion: use void __iomem pointers for UART registration functions arm: mach-mvebu: use IOMEM() for base address definitions arm: mach-orion5x: use IOMEM() for base address definitions arm: mach-mv78xx0: use IOMEM() for base address definitions arm: mach-kirkwood: use IOMEM() for base address definitions arm: mach-dove: use IOMEM() for base address definitions arm: mach-orion5x: use plus instead of or for address definitions arm: mach-mv78xx0: use plus instead of or for address definitions arm: mach-kirkwood: use plus instead of or for address definitions arm: mach-dove: use plus instead of or for address definitions This branch had quite a few conflicts, in particular with the PCI static map rework from Rob Herring, and a few other context conflicts due to changes in Kconfig, etc. I fixed up conflicts in: arch/arm/Kconfig arch/arm/mach-dove/common.c arch/arm/mach-dove/include/mach/dove.h arch/arm/mach-kirkwood/common.c arch/arm/mach-kirkwood/include/mach/kirkwood.h arch/arm/mach-mv78xx0/common.c arch/arm/mach-mv78xx0/include/mach/mv78xx0.h arch/arm/mach-orion5x/common.c arch/arm/mach-orion5x/include/mach/orion5x.h Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-dove')
-rw-r--r--arch/arm/mach-dove/common.c4
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h16
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h126
-rw-r--r--arch/arm/mach-dove/irq.c10
-rw-r--r--arch/arm/mach-dove/pcie.c6
5 files changed, 81 insertions, 81 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 28475bb7d36f..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -41,12 +41,12 @@
41 ****************************************************************************/ 41 ****************************************************************************/
42static struct map_desc dove_io_desc[] __initdata = { 42static struct map_desc dove_io_desc[] __initdata = {
43 { 43 {
44 .virtual = DOVE_SB_REGS_VIRT_BASE, 44 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
46 .length = DOVE_SB_REGS_SIZE, 46 .length = DOVE_SB_REGS_SIZE,
47 .type = MT_DEVICE, 47 .type = MT_DEVICE,
48 }, { 48 }, {
49 .virtual = DOVE_NB_REGS_VIRT_BASE, 49 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
51 .length = DOVE_NB_REGS_SIZE, 51 .length = DOVE_NB_REGS_SIZE,
52 .type = MT_DEVICE, 52 .type = MT_DEVICE,
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
13 13
14#include <mach/dove.h> 14#include <mach/dove.h>
15 15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) 16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
17 17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) 18#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001 19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002 20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008 21#define CPU_CTRL_PCIE1_LINK 0x00000008
22 22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004 24#define SOFT_RESET_OUT_EN 0x00000004
25 25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27#define SOFT_RESET 0x00000001 27#define SOFT_RESET 0x00000001
28 28
29#define BRIDGE_INT_TIMER1_CLR (~0x0004) 29#define BRIDGE_INT_TIMER1_CLR (~0x0004)
30 30
31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
32#define IRQ_CAUSE_LOW_OFF 0x0000 32#define IRQ_CAUSE_LOW_OFF 0x0000
33#define IRQ_MASK_LOW_OFF 0x0004 33#define IRQ_MASK_LOW_OFF 0x0004
34#define FIQ_MASK_LOW_OFF 0x0008 34#define FIQ_MASK_LOW_OFF 0x0008
@@ -47,9 +47,9 @@
47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
49 49
50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) 50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
51 51
52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) 52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
53#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) 53#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
54 54
55#endif 55#endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index c91e3004a47b..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
25 */ 25 */
26 26
27#define DOVE_CESA_PHYS_BASE 0xc8000000 27#define DOVE_CESA_PHYS_BASE 0xc8000000
28#define DOVE_CESA_VIRT_BASE 0xfdb00000 28#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
29#define DOVE_CESA_SIZE SZ_1M 29#define DOVE_CESA_SIZE SZ_1M
30 30
31#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 31#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
@@ -38,15 +38,15 @@
38#define DOVE_BOOTROM_SIZE SZ_128M 38#define DOVE_BOOTROM_SIZE SZ_128M
39 39
40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 41#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
42#define DOVE_SCRATCHPAD_SIZE SZ_1M 42#define DOVE_SCRATCHPAD_SIZE SZ_1M
43 43
44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
45#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 45#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
46#define DOVE_SB_REGS_SIZE SZ_8M 46#define DOVE_SB_REGS_SIZE SZ_8M
47 47
48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
49#define DOVE_NB_REGS_VIRT_BASE 0xfe600000 49#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
50#define DOVE_NB_REGS_SIZE SZ_8M 50#define DOVE_NB_REGS_SIZE SZ_8M
51 51
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
@@ -62,75 +62,75 @@
62 */ 62 */
63 63
64/* SPI, I2C, UART */ 64/* SPI, I2C, UART */
65#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) 65#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
66#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) 66#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
67#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) 67#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
68#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) 68#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
69#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) 69#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
70#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) 70#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
71#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) 71#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
72#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) 72#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
73#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) 73#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
74#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) 74#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
75#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) 75#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
76 76
77/* North-South Bridge */ 77/* North-South Bridge */
78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) 78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000) 79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80 80
81/* Cryptographic Engine */ 81/* Cryptographic Engine */
82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) 82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
83 83
84/* PCIe 0 */ 84/* PCIe 0 */
85#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) 85#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
86 86
87/* USB */ 87/* USB */
88#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) 88#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
89#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) 89#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
90 90
91/* XOR 0 Engine */ 91/* XOR 0 Engine */
92#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) 92#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
93#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) 93#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
94#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) 94#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
95#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) 95#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
96 96
97/* XOR 1 Engine */ 97/* XOR 1 Engine */
98#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) 98#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
99#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) 99#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
100#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) 100#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
101#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) 101#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
102 102
103/* Gigabit Ethernet */ 103/* Gigabit Ethernet */
104#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) 104#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
105 105
106/* PCIe 1 */ 106/* PCIe 1 */
107#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) 107#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
108 108
109/* CAFE */ 109/* CAFE */
110#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) 110#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
111#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) 111#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
112#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) 112#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
113#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) 113#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
114 114
115/* SATA */ 115/* SATA */
116#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) 116#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
117 117
118/* I2S/SPDIF */ 118/* I2S/SPDIF */
119#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) 119#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
120#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) 120#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
121 121
122/* NAND Flash Controller */ 122/* NAND Flash Controller */
123#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) 123#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
124 124
125/* MPP, GPIO, Reset Sampling */ 125/* MPP, GPIO, Reset Sampling */
126#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) 126#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
127#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 127#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
128#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) 128#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
129#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) 129#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
130#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) 130#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
131#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420) 131#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
132#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) 132#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
133#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 133#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
134#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 134#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
135#define DOVE_NAND_GPIO_EN (1 << 0) 135#define DOVE_NAND_GPIO_EN (1 << 0)
136#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 136#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
142#define DOVE_SD0_GPIO_SEL (1 << 0) 142#define DOVE_SD0_GPIO_SEL (1 << 0)
143 143
144/* Power Management */ 144/* Power Management */
145#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) 145#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
146#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) 146#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
147 147
148/* Real Time Clock */ 148/* Real Time Clock */
149#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) 149#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
150 150
151/* AC97 */ 151/* AC97 */
152#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) 152#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
153#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) 153#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
154 154
155/* Peripheral DMA */ 155/* Peripheral DMA */
156#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) 156#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
157#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) 157#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
158 158
159#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) 159#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
160#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) 160#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
161#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) 161#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
162#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) 162#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
163#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) 163#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
164#define DOVE_TWSI_OPTION3_GPIO (1 << 22) 164#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
165#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) 165#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
166#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) 166#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
167#define DOVE_SSP_ON_AU1 (1 << 0) 167#define DOVE_SSP_ON_AU1 (1 << 0)
168#define DOVE_SSP_CLOCK_ENABLE (1 << 1) 168#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170/* Memory Controller */ 170/* Memory Controller */
171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) 171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
172 172
173/* LCD Controller */ 173/* LCD Controller */
174#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) 174#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
175#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) 175#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
176#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) 176#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
177#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) 177#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
178 178
179/* Graphic Engine */ 179/* Graphic Engine */
180#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) 180#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
181 181
182/* Video Engine */ 182/* Video Engine */
183#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) 183#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
184 184
185#endif 185#endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 186357f3b4db..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -100,19 +100,19 @@ void __init dove_init_irq(void)
100{ 100{
101 int i; 101 int i;
102 102
103 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 103 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
104 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 104 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
105 105
106 /* 106 /*
107 * Initialize gpiolib for GPIOs 0-71. 107 * Initialize gpiolib for GPIOs 0-71.
108 */ 108 */
109 orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0, 109 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
110 IRQ_DOVE_GPIO_START, gpio0_irqs); 110 IRQ_DOVE_GPIO_START, gpio0_irqs);
111 111
112 orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0, 112 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs); 113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
114 114
115 orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0, 115 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs); 116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
117 117
118 /* 118 /*
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 355332d502cb..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
182 .map_irq = dove_pcie_map_irq, 182 .map_irq = dove_pcie_map_irq,
183}; 183};
184 184
185static void __init add_pcie_port(int index, unsigned long base) 185static void __init add_pcie_port(int index, void __iomem *base)
186{ 186{
187 printk(KERN_INFO "Dove PCIe port %d: ", index); 187 printk(KERN_INFO "Dove PCIe port %d: ", index);
188 188
189 if (orion_pcie_link_up((void __iomem *)base)) { 189 if (orion_pcie_link_up(base)) {
190 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 190 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
191 191
192 printk(KERN_INFO "link up\n"); 192 printk(KERN_INFO "link up\n");
193 193
194 pp->index = index; 194 pp->index = index;
195 pp->root_bus_nr = -1; 195 pp->root_bus_nr = -1;
196 pp->base = (void __iomem *)base; 196 pp->base = base;
197 spin_lock_init(&pp->conf_lock); 197 spin_lock_init(&pp->conf_lock);
198 memset(&pp->res, 0, sizeof(pp->res)); 198 memset(&pp->res, 0, sizeof(pp->res));
199 } else { 199 } else {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 17:59:58 -0500