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authorDavid Griego <dgriego@mvista.com>2009-06-01 14:41:54 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-08-26 03:56:56 -0400
commita23f7dc82d48d7fc8377765f6ede907daef4e63b (patch)
tree2159e2885ae764e70f616faa945c24771c5e86c0 /arch/arm/mach-davinci/time.c
parent75d0fa70e748629b786c25530f7c5ae76587da35 (diff)
davinci: Fix watchdog reset code
The davinci reset routine, davinci_watchdog_reset(), sets the TCR register instead of the TGCR register as it should to put the WDT into its "Initial State". It also writes the WDTCR register without the proper WDKEY which is pointless since the register will be write-protected. Signed-off-by: David Griego <dgriego@mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/time.c')
-rw-r--r--arch/arm/mach-davinci/time.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0884ca57bfb0..ca85d1871762 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -420,11 +420,11 @@ void davinci_watchdog_reset(void)
420 420
421 /* reset timer, set mode to 64-bit watchdog, and unreset */ 421 /* reset timer, set mode to 64-bit watchdog, and unreset */
422 tgcr = 0; 422 tgcr = 0;
423 __raw_writel(tgcr, base + TCR); 423 __raw_writel(tgcr, base + TGCR);
424 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; 424 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
425 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 425 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
426 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 426 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
427 __raw_writel(tgcr, base + TCR); 427 __raw_writel(tgcr, base + TGCR);
428 428
429 /* clear counter and period regs */ 429 /* clear counter and period regs */
430 __raw_writel(0, base + TIM12); 430 __raw_writel(0, base + TIM12);
@@ -432,12 +432,8 @@ void davinci_watchdog_reset(void)
432 __raw_writel(0, base + PRD12); 432 __raw_writel(0, base + PRD12);
433 __raw_writel(0, base + PRD34); 433 __raw_writel(0, base + PRD34);
434 434
435 /* enable */
436 wdtcr = __raw_readl(base + WDTCR);
437 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
438 __raw_writel(wdtcr, base + WDTCR);
439
440 /* put watchdog in pre-active state */ 435 /* put watchdog in pre-active state */
436 wdtcr = __raw_readl(base + WDTCR);
441 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | 437 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
442 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 438 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
443 __raw_writel(wdtcr, base + WDTCR); 439 __raw_writel(wdtcr, base + WDTCR);