diff options
| author | Anton Vorontsov <avorontsov@mvista.com> | 2010-06-02 06:12:08 -0400 |
|---|---|---|
| committer | Anton Vorontsov <avorontsov@mvista.com> | 2010-06-08 09:31:29 -0400 |
| commit | 6eb5d146d4535822d32cb317df5a9e37da6e31f6 (patch) | |
| tree | 2022261146cbfbdbf149fea4e9b43d99843e5515 /arch/arm/mach-cns3xxx/include | |
| parent | 9dda696f0de87a2e5cfabb147e28c76b7d3c6846 (diff) | |
ARM: cns3xxx: Use IO memory accessors everywhere
Before it isn't too late let's switch to IO memory accessors.
This patch converts all current _REG users and _REG definitions.
There should be no functional changes.
Suggested-by: Ben Dooks <ben-linux@fluff.org>
Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
Diffstat (limited to 'arch/arm/mach-cns3xxx/include')
| -rw-r--r-- | arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | 91 |
1 files changed, 45 insertions, 46 deletions
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 8a2f5a21d4ee..6dbce13771ca 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | |||
| @@ -247,37 +247,36 @@ | |||
| 247 | * Misc block | 247 | * Misc block |
| 248 | */ | 248 | */ |
| 249 | #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) | 249 | #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) |
| 250 | #define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) | 250 | |
| 251 | 251 | #define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) | |
| 252 | #define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) | 252 | #define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) |
| 253 | #define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) | 253 | #define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) |
| 254 | #define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) | 254 | #define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) |
| 255 | #define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) | 255 | #define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) |
| 256 | #define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) | 256 | #define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) |
| 257 | #define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) | 257 | #define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) |
| 258 | #define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) | 258 | #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) |
| 259 | #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) | 259 | #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) |
| 260 | #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) | 260 | #define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) |
| 261 | #define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) | 261 | #define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) |
| 262 | #define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) | 262 | #define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) |
| 263 | #define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) | 263 | #define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) |
| 264 | #define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) | 264 | #define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) |
| 265 | #define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) | 265 | #define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) |
| 266 | #define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) | 266 | #define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) |
| 267 | #define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) | 267 | #define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) |
| 268 | #define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) | 268 | #define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) |
| 269 | #define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) | 269 | #define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) |
| 270 | #define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) | 270 | #define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) |
| 271 | #define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) | 271 | |
| 272 | 272 | #define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) | |
| 273 | #define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) | 273 | |
| 274 | 274 | #define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) | |
| 275 | #define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) | 275 | #define MISC_USB_STS_REG MISC_MEM_MAP(0x804) |
| 276 | #define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) | 276 | #define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) |
| 277 | #define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) | 277 | #define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) |
| 278 | #define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) | 278 | #define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) |
| 279 | #define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) | 279 | #define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) |
| 280 | #define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814) | ||
| 281 | 280 | ||
| 282 | #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) | 281 | #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) |
| 283 | #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) | 282 | #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) |
| @@ -300,21 +299,21 @@ | |||
| 300 | /* | 299 | /* |
| 301 | * Power management and clock control | 300 | * Power management and clock control |
| 302 | */ | 301 | */ |
| 303 | #define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) | 302 | #define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) |
| 304 | 303 | ||
| 305 | #define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) | 304 | #define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) |
| 306 | #define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) | 305 | #define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) |
| 307 | #define PM_HS_CFG_REG PMU_REG_VALUE(0x008) | 306 | #define PM_HS_CFG_REG PMU_MEM_MAP(0x008) |
| 308 | #define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) | 307 | #define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) |
| 309 | #define PM_PWR_STA_REG PMU_REG_VALUE(0x010) | 308 | #define PM_PWR_STA_REG PMU_MEM_MAP(0x010) |
| 310 | #define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) | 309 | #define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) |
| 311 | #define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) | 310 | #define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) |
| 312 | #define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) | 311 | #define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) |
| 313 | #define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) | 312 | #define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) |
| 314 | #define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) | 313 | #define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) |
| 315 | #define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) | 314 | #define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) |
| 316 | #define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) | 315 | #define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) |
| 317 | #define PM_CSR_REG PMU_REG_VALUE(0x030) | 316 | #define PM_CSR_REG PMU_MEM_MAP(0x030) |
| 318 | 317 | ||
| 319 | /* PM_CLK_GATE_REG */ | 318 | /* PM_CLK_GATE_REG */ |
| 320 | #define PM_CLK_GATE_REG_OFFSET_SDIO (25) | 319 | #define PM_CLK_GATE_REG_OFFSET_SDIO (25) |