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authorNicolas Ferre <nicolas.ferre@atmel.com>2009-03-31 12:13:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-04-28 17:44:55 -0400
commit6d0485a99366d4e0e7e725f14995c74cb7ca4499 (patch)
tree04c3551d9af2cf784e67fb06720d16a2fdc5b9cb /arch/arm/mach-at91/clock.c
parentb4175b89921fefb2f352472fa6dccb0fc4fb37d9 (diff)
[ARM] 5438/1: AT91: manage clock by functionality instead of CPUs
In clock.c file the clock management is grouped by cpu with cpu_is_xxx() function. This lead to some kind of difficulties to read this file and maintainability issues as the number of AT91 cpus & PLLs/clocks is growing. In this patch, I try to group clock functionality together and match cpus with this functionality set. An update to at91_pmc.h is needed to cover some new PMC possibilities (and some update in comments). Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <avictor.za@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/clock.c')
-rw-r--r--arch/arm/mach-at91/clock.c151
1 files changed, 112 insertions, 39 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index e4345106ee57..bac578fe0d3d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -43,6 +43,25 @@
43#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) 43#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
44 44
45 45
46/*
47 * Chips have some kind of clocks : group them by functionality
48 */
49#define cpu_has_utmi() ( cpu_is_at91cap9() \
50 || cpu_is_at91sam9rl())
51
52#define cpu_has_800M_plla() (cpu_is_at91sam9g20())
53
54#define cpu_has_pllb() (!cpu_is_at91sam9rl())
55
56#define cpu_has_upll() (0)
57
58/* USB host HS & FS */
59#define cpu_has_uhp() (!cpu_is_at91sam9rl())
60
61/* USB device FS only */
62#define cpu_has_udpfs() (!cpu_is_at91sam9rl())
63
64
46static LIST_HEAD(clocks); 65static LIST_HEAD(clocks);
47static DEFINE_SPINLOCK(clk_lock); 66static DEFINE_SPINLOCK(clk_lock);
48 67
@@ -140,7 +159,7 @@ static struct clk utmi_clk = {
140}; 159};
141static struct clk uhpck = { 160static struct clk uhpck = {
142 .name = "uhpck", 161 .name = "uhpck",
143 .parent = &pllb, 162 /*.parent = ... we choose parent at runtime */
144 .mode = pmc_sys_mode, 163 .mode = pmc_sys_mode,
145}; 164};
146 165
@@ -173,7 +192,11 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
173 case AT91_PMC_CSS_PLLA: 192 case AT91_PMC_CSS_PLLA:
174 return &plla; 193 return &plla;
175 case AT91_PMC_CSS_PLLB: 194 case AT91_PMC_CSS_PLLB:
176 return &pllb; 195 if (cpu_has_upll())
196 /* CSS_PLLB == CSS_UPLL */
197 return &utmi_clk;
198 else if (cpu_has_pllb())
199 return &pllb;
177 } 200 }
178 201
179 return NULL; 202 return NULL;
@@ -322,7 +345,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
322 u32 pckr; 345 u32 pckr;
323 346
324 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 347 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
325 pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ 348 pckr &= AT91_PMC_CSS; /* clock selection */
326 pckr |= prescale << 2; 349 pckr |= prescale << 2;
327 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); 350 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
328 clk->rate_hz = actual; 351 clk->rate_hz = actual;
@@ -361,7 +384,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
361} 384}
362EXPORT_SYMBOL(clk_set_parent); 385EXPORT_SYMBOL(clk_set_parent);
363 386
364/* establish PCK0..PCK3 parentage and rate */ 387/* establish PCK0..PCKN parentage and rate */
365static void __init init_programmable_clock(struct clk *clk) 388static void __init init_programmable_clock(struct clk *clk)
366{ 389{
367 struct clk *parent; 390 struct clk *parent;
@@ -389,11 +412,13 @@ static int at91_clk_show(struct seq_file *s, void *unused)
389 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); 412 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
390 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); 413 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
391 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); 414 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
392 if (!cpu_is_at91sam9rl()) 415 if (cpu_has_pllb())
393 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); 416 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
394 if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) 417 if (cpu_has_utmi())
395 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); 418 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
396 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); 419 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
420 if (cpu_has_upll())
421 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
397 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); 422 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
398 423
399 seq_printf(s, "\n"); 424 seq_printf(s, "\n");
@@ -554,16 +579,60 @@ static struct clk *const standard_pmc_clocks[] __initdata = {
554 &clk32k, 579 &clk32k,
555 &main_clk, 580 &main_clk,
556 &plla, 581 &plla,
557 &pllb,
558
559 /* PLLB children (USB) */
560 &udpck,
561 &uhpck,
562 582
563 /* MCK */ 583 /* MCK */
564 &mck 584 &mck
565}; 585};
566 586
587/* PLLB generated USB full speed clock init */
588static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
589{
590 /*
591 * USB clock init: choose 48 MHz PLLB value,
592 * disable 48MHz clock during usb peripheral suspend.
593 *
594 * REVISIT: assumes MCK doesn't derive from PLLB!
595 */
596 uhpck.parent = &pllb;
597
598 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
599 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
600 if (cpu_is_at91rm9200()) {
601 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
602 udpck.pmc_mask = AT91RM9200_PMC_UDP;
603 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
604 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
605 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
606 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
607 } else if (cpu_is_at91cap9()) {
608 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
609 }
610 at91_sys_write(AT91_CKGR_PLLBR, 0);
611
612 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
613 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
614}
615
616/* UPLL generated USB full speed clock init */
617static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
618{
619 /*
620 * USB clock init: choose 480 MHz from UPLL,
621 */
622 unsigned int usbr = AT91_PMC_USBS_UPLL;
623
624 /* Setup divider by 10 to reach 48 MHz */
625 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
626
627 at91_sys_write(AT91_PMC_USB, usbr);
628
629 /* Now set uhpck values */
630 uhpck.parent = &utmi_clk;
631 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
632 uhpck.rate_hz = utmi_clk.parent->rate_hz;
633 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
634}
635
567int __init at91_clock_init(unsigned long main_clock) 636int __init at91_clock_init(unsigned long main_clock)
568{ 637{
569 unsigned tmp, freq, mckr; 638 unsigned tmp, freq, mckr;
@@ -585,43 +654,37 @@ int __init at91_clock_init(unsigned long main_clock)
585 654
586 /* report if PLLA is more than mildly overclocked */ 655 /* report if PLLA is more than mildly overclocked */
587 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); 656 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
588 if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) 657 if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000)
589 || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) 658 || (cpu_has_800M_plla() && plla.rate_hz > 800000000))
590 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); 659 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
591 660
592 /* 661
593 * USB clock init: choose 48 MHz PLLB value, 662 if (cpu_has_upll() && !cpu_has_pllb()) {
594 * disable 48MHz clock during usb peripheral suspend. 663 /* setup UTMI clock as the fourth primary clock
595 * 664 * (instead of pllb) */
596 * REVISIT: assumes MCK doesn't derive from PLLB! 665 utmi_clk.type |= CLK_TYPE_PRIMARY;
597 */ 666 utmi_clk.id = 3;
598 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
599 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
600 if (cpu_is_at91rm9200()) {
601 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
602 udpck.pmc_mask = AT91RM9200_PMC_UDP;
603 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
604 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
605 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
606 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
607 } else if (cpu_is_at91cap9()) {
608 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
609 } 667 }
610 at91_sys_write(AT91_CKGR_PLLBR, 0);
611 668
612 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
613 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
614 669
615 /* 670 /*
616 * USB HS clock init 671 * USB HS clock init
617 */ 672 */
618 if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { 673 if (cpu_has_utmi())
619 /* 674 /*
620 * multiplier is hard-wired to 40 675 * multiplier is hard-wired to 40
621 * (obtain the USB High Speed 480 MHz when input is 12 MHz) 676 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
622 */ 677 */
623 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; 678 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
624 } 679
680 /*
681 * USB FS clock init
682 */
683 if (cpu_has_pllb())
684 at91_pllb_usbfs_clock_init(main_clock);
685 if (cpu_has_upll())
686 /* assumes that we choose UPLL for USB and not PLLA */
687 at91_upll_usbfs_clock_init(main_clock);
625 688
626 /* 689 /*
627 * MCK and CPU derive from one of those primary clocks. 690 * MCK and CPU derive from one of those primary clocks.
@@ -631,21 +694,31 @@ int __init at91_clock_init(unsigned long main_clock)
631 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); 694 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
632 freq = mck.parent->rate_hz; 695 freq = mck.parent->rate_hz;
633 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ 696 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
634 if (cpu_is_at91rm9200()) 697 if (cpu_is_at91rm9200()) {
635 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 698 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
636 else if (cpu_is_at91sam9g20()) { 699 } else if (cpu_is_at91sam9g20()) {
637 mck.rate_hz = (mckr & AT91_PMC_MDIV) ? 700 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
638 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ 701 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
639 if (mckr & AT91_PMC_PDIV) 702 if (mckr & AT91_PMC_PDIV)
640 freq /= 2; /* processor clock division */ 703 freq /= 2; /* processor clock division */
641 } else 704 } else {
642 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 705 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
706 }
643 707
644 /* Register the PMC's standard clocks */ 708 /* Register the PMC's standard clocks */
645 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) 709 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
646 list_add_tail(&standard_pmc_clocks[i]->node, &clocks); 710 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
647 711
648 if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) 712 if (cpu_has_pllb())
713 list_add_tail(&pllb.node, &clocks);
714
715 if (cpu_has_uhp())
716 list_add_tail(&uhpck.node, &clocks);
717
718 if (cpu_has_udpfs())
719 list_add_tail(&udpck.node, &clocks);
720
721 if (cpu_has_utmi())
649 list_add_tail(&utmi_clk.node, &clocks); 722 list_add_tail(&utmi_clk.node, &clocks);
650 723
651 /* MCK and CPU clock are "always on" */ 724 /* MCK and CPU clock are "always on" */