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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:23:24 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:23:24 -0400
commit9bc747bea5fad819e0c0ad96e6a67ea0640dfe2b (patch)
treed500225e7a1c90a6bd17d3e63e2f6e781810db2b /arch/arm/include/asm/hardware
parent32b908eea9e5ecd1049008e134eadbfcd0da5e38 (diff)
parent0e896b1ddc1905df904df98c204bacf028219729 (diff)
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull first batch of arm-soc cleanups from Olof Johansson: "These cleanups are basically all over the place. The idea is to collect changes with minimal impact but large number of changes so we can avoid them from distracting in the diffstat in the other series. A significant number of lines get removed here, in particular because the ixp2000 and ixp23xx platforms get removed. These have never been extremely popular and have fallen into disuse over time with no active maintainer taking care of them. The u5500 soc never made it into a product, so we are removing it from the ux500 platform. Many good cleanups also went into the at91 and omap platforms, as has been the case for a number of releases." Trivial modify-delete conflicts in arch/arm/mach-{ixp2000,ixp23xx} * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (152 commits) ARM: clps711x: Cleanup IRQ handling ARM clps711x: Removed unused header mach/time.h ARM: clps711x: Added note about support EP731x CPU to Kconfig ARM: clps711x: Added missing register definitions ARM: clps711x: Used own subarch directory for store header file Dove: Fix Section mismatch warnings ARM: orion5x: ts78xx debugging changes ARM: orion5x: remove PM dependency from ts78xx ARM: orion5x: ts78xx fix NAND resource off by one ARM: orion5x: ts78xx whitespace cleanups Orion5x: Fix Section mismatch warnings Orion5x: Fix warning: struct pci_dev declared inside paramter list ARM: clps711x: Combine header files into one for clps711x-targets ARM: S3C24XX: Use common macro to define resources on mach-qt2410.c ARM: S3C24XX: Use common macro to define resources on mach-osiris.c ARM: EXYNOS: Adapt to cpuidle core time keeping and irq enable ARM: S5PV210: Use common macro to define resources on mach-smdkv210.c ARM: S5PV210: Use common macro to define resources on dev-audio.c ARM: S5PC100: Use common macro to define resources on dev-audio.c ARM: S5P64X0: Use common macro to define resources on dev-audio.c ...
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r--arch/arm/include/asm/hardware/clps7111.h184
-rw-r--r--arch/arm/include/asm/hardware/cs89712.h49
-rw-r--r--arch/arm/include/asm/hardware/ep7211.h40
-rw-r--r--arch/arm/include/asm/hardware/ep7212.h83
-rw-r--r--arch/arm/include/asm/hardware/uengine.h62
5 files changed, 0 insertions, 418 deletions
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h
deleted file mode 100644
index 44477225aed6..000000000000
--- a/arch/arm/include/asm/hardware/clps7111.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/clps7111.h
3 *
4 * This file contains the hardware definitions of the CLPS7111 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_CLPS7111_H
24#define __ASM_HARDWARE_CLPS7111_H
25
26#define CLPS7111_PHYS_BASE (0x80000000)
27
28#ifndef __ASSEMBLY__
29#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
30#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
31#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
32#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
33#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
34#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
35#endif
36
37#define PADR (0x0000)
38#define PBDR (0x0001)
39#define PDDR (0x0003)
40#define PADDR (0x0040)
41#define PBDDR (0x0041)
42#define PDDDR (0x0043)
43#define PEDR (0x0080)
44#define PEDDR (0x00c0)
45#define SYSCON1 (0x0100)
46#define SYSFLG1 (0x0140)
47#define MEMCFG1 (0x0180)
48#define MEMCFG2 (0x01c0)
49#define DRFPR (0x0200)
50#define INTSR1 (0x0240)
51#define INTMR1 (0x0280)
52#define LCDCON (0x02c0)
53#define TC1D (0x0300)
54#define TC2D (0x0340)
55#define RTCDR (0x0380)
56#define RTCMR (0x03c0)
57#define PMPCON (0x0400)
58#define CODR (0x0440)
59#define UARTDR1 (0x0480)
60#define UBRLCR1 (0x04c0)
61#define SYNCIO (0x0500)
62#define PALLSW (0x0540)
63#define PALMSW (0x0580)
64#define STFCLR (0x05c0)
65#define BLEOI (0x0600)
66#define MCEOI (0x0640)
67#define TEOI (0x0680)
68#define TC1EOI (0x06c0)
69#define TC2EOI (0x0700)
70#define RTCEOI (0x0740)
71#define UMSEOI (0x0780)
72#define COEOI (0x07c0)
73#define HALT (0x0800)
74#define STDBY (0x0840)
75
76#define FBADDR (0x1000)
77#define SYSCON2 (0x1100)
78#define SYSFLG2 (0x1140)
79#define INTSR2 (0x1240)
80#define INTMR2 (0x1280)
81#define UARTDR2 (0x1480)
82#define UBRLCR2 (0x14c0)
83#define SS2DR (0x1500)
84#define SRXEOF (0x1600)
85#define SS2POP (0x16c0)
86#define KBDEOI (0x1700)
87
88/* common bits: SYSCON1 / SYSCON2 */
89#define SYSCON_UARTEN (1 << 8)
90
91#define SYSCON1_KBDSCAN(x) ((x) & 15)
92#define SYSCON1_KBDSCANMASK (15)
93#define SYSCON1_TC1M (1 << 4)
94#define SYSCON1_TC1S (1 << 5)
95#define SYSCON1_TC2M (1 << 6)
96#define SYSCON1_TC2S (1 << 7)
97#define SYSCON1_UART1EN SYSCON_UARTEN
98#define SYSCON1_BZTOG (1 << 9)
99#define SYSCON1_BZMOD (1 << 10)
100#define SYSCON1_DBGEN (1 << 11)
101#define SYSCON1_LCDEN (1 << 12)
102#define SYSCON1_CDENTX (1 << 13)
103#define SYSCON1_CDENRX (1 << 14)
104#define SYSCON1_SIREN (1 << 15)
105#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
106#define SYSCON1_ADCKSEL_MASK (3 << 16)
107#define SYSCON1_EXCKEN (1 << 18)
108#define SYSCON1_WAKEDIS (1 << 19)
109#define SYSCON1_IRTXM (1 << 20)
110
111/* common bits: SYSFLG1 / SYSFLG2 */
112#define SYSFLG_UBUSY (1 << 11)
113#define SYSFLG_URXFE (1 << 22)
114#define SYSFLG_UTXFF (1 << 23)
115
116#define SYSFLG1_MCDR (1 << 0)
117#define SYSFLG1_DCDET (1 << 1)
118#define SYSFLG1_WUDR (1 << 2)
119#define SYSFLG1_WUON (1 << 3)
120#define SYSFLG1_CTS (1 << 8)
121#define SYSFLG1_DSR (1 << 9)
122#define SYSFLG1_DCD (1 << 10)
123#define SYSFLG1_UBUSY SYSFLG_UBUSY
124#define SYSFLG1_NBFLG (1 << 12)
125#define SYSFLG1_RSTFLG (1 << 13)
126#define SYSFLG1_PFFLG (1 << 14)
127#define SYSFLG1_CLDFLG (1 << 15)
128#define SYSFLG1_URXFE SYSFLG_URXFE
129#define SYSFLG1_UTXFF SYSFLG_UTXFF
130#define SYSFLG1_CRXFE (1 << 24)
131#define SYSFLG1_CTXFF (1 << 25)
132#define SYSFLG1_SSIBUSY (1 << 26)
133#define SYSFLG1_ID (1 << 29)
134
135#define SYSFLG2_SSRXOF (1 << 0)
136#define SYSFLG2_RESVAL (1 << 1)
137#define SYSFLG2_RESFRM (1 << 2)
138#define SYSFLG2_SS2RXFE (1 << 3)
139#define SYSFLG2_SS2TXFF (1 << 4)
140#define SYSFLG2_SS2TXUF (1 << 5)
141#define SYSFLG2_CKMODE (1 << 6)
142#define SYSFLG2_UBUSY SYSFLG_UBUSY
143#define SYSFLG2_URXFE SYSFLG_URXFE
144#define SYSFLG2_UTXFF SYSFLG_UTXFF
145
146#define LCDCON_GSEN (1 << 30)
147#define LCDCON_GSMD (1 << 31)
148
149#define SYSCON2_SERSEL (1 << 0)
150#define SYSCON2_KBD6 (1 << 1)
151#define SYSCON2_DRAMZ (1 << 2)
152#define SYSCON2_KBWEN (1 << 3)
153#define SYSCON2_SS2TXEN (1 << 4)
154#define SYSCON2_PCCARD1 (1 << 5)
155#define SYSCON2_PCCARD2 (1 << 6)
156#define SYSCON2_SS2RXEN (1 << 7)
157#define SYSCON2_UART2EN SYSCON_UARTEN
158#define SYSCON2_SS2MAEN (1 << 9)
159#define SYSCON2_OSTB (1 << 12)
160#define SYSCON2_CLKENSL (1 << 13)
161#define SYSCON2_BUZFREQ (1 << 14)
162
163/* common bits: UARTDR1 / UARTDR2 */
164#define UARTDR_FRMERR (1 << 8)
165#define UARTDR_PARERR (1 << 9)
166#define UARTDR_OVERR (1 << 10)
167
168/* common bits: UBRLCR1 / UBRLCR2 */
169#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
170#define UBRLCR_BREAK (1 << 12)
171#define UBRLCR_PRTEN (1 << 13)
172#define UBRLCR_EVENPRT (1 << 14)
173#define UBRLCR_XSTOP (1 << 15)
174#define UBRLCR_FIFOEN (1 << 16)
175#define UBRLCR_WRDLEN5 (0 << 17)
176#define UBRLCR_WRDLEN6 (1 << 17)
177#define UBRLCR_WRDLEN7 (2 << 17)
178#define UBRLCR_WRDLEN8 (3 << 17)
179#define UBRLCR_WRDLEN_MASK (3 << 17)
180
181#define SYNCIO_SMCKEN (1 << 13)
182#define SYNCIO_TXFRMEN (1 << 14)
183
184#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/arch/arm/include/asm/hardware/cs89712.h b/arch/arm/include/asm/hardware/cs89712.h
deleted file mode 100644
index f75626933e94..000000000000
--- a/arch/arm/include/asm/hardware/cs89712.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/cs89712.h
3 *
4 * This file contains the hardware definitions of the CS89712
5 * additional internal registers.
6 *
7 * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __ASM_HARDWARE_CS89712_H
25#define __ASM_HARDWARE_CS89712_H
26
27/*
28* CS89712 additional registers
29*/
30
31#define PCDR 0x0002 /* Port C Data register ---------------------------- */
32#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
33#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
34#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
35
36#define SDCONF_ACTIVE (1 << 10)
37#define SDCONF_CLKCTL (1 << 9)
38#define SDCONF_WIDTH_4 (0 << 7)
39#define SDCONF_WIDTH_8 (1 << 7)
40#define SDCONF_WIDTH_16 (2 << 7)
41#define SDCONF_WIDTH_32 (3 << 7)
42#define SDCONF_SIZE_16 (0 << 5)
43#define SDCONF_SIZE_64 (1 << 5)
44#define SDCONF_SIZE_128 (2 << 5)
45#define SDCONF_SIZE_256 (3 << 5)
46#define SDCONF_CASLAT_2 (2)
47#define SDCONF_CASLAT_3 (3)
48
49#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h
deleted file mode 100644
index 654d5f625c49..000000000000
--- a/arch/arm/include/asm/hardware/ep7211.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/ep7211.h
3 *
4 * This file contains the hardware definitions of the EP7211 internal
5 * registers.
6 *
7 * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7211_H
24#define __ASM_HARDWARE_EP7211_H
25
26#include <asm/hardware/clps7111.h>
27
28/*
29 * define EP7211_BASE to be the base address of the region
30 * you want to access.
31 */
32
33#define EP7211_PHYS_BASE (0x80000000)
34
35/*
36 * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
37 * present in 7212) here.
38 */
39
40#endif /* __ASM_HARDWARE_EP7211_H */
diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h
deleted file mode 100644
index 3b43bbeaf1db..000000000000
--- a/arch/arm/include/asm/hardware/ep7212.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/ep7212.h
3 *
4 * This file contains the hardware definitions of the EP7212 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7212_H
24#define __ASM_HARDWARE_EP7212_H
25
26/*
27 * define EP7212_BASE to be the base address of the region
28 * you want to access.
29 */
30
31#define EP7212_PHYS_BASE (0x80000000)
32
33#ifndef __ASSEMBLY__
34#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
35#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
36#endif
37
38/*
39 * These registers are specific to the EP7212 only
40 */
41#define DAIR 0x2000
42#define DAIR0 0x2040
43#define DAIDR1 0x2080
44#define DAIDR2 0x20c0
45#define DAISR 0x2100
46#define SYSCON3 0x2200
47#define INTSR3 0x2240
48#define INTMR3 0x2280
49#define LEDFLSH 0x22c0
50
51#define DAIR_DAIEN (1 << 16)
52#define DAIR_ECS (1 << 17)
53#define DAIR_LCTM (1 << 19)
54#define DAIR_LCRM (1 << 20)
55#define DAIR_RCTM (1 << 21)
56#define DAIR_RCRM (1 << 22)
57#define DAIR_LBM (1 << 23)
58
59#define DAIDR2_FIFOEN (1 << 15)
60#define DAIDR2_FIFOLEFT (0x0d << 16)
61#define DAIDR2_FIFORIGHT (0x11 << 16)
62
63#define DAISR_RCTS (1 << 0)
64#define DAISR_RCRS (1 << 1)
65#define DAISR_LCTS (1 << 2)
66#define DAISR_LCRS (1 << 3)
67#define DAISR_RCTU (1 << 4)
68#define DAISR_RCRO (1 << 5)
69#define DAISR_LCTU (1 << 6)
70#define DAISR_LCRO (1 << 7)
71#define DAISR_RCNF (1 << 8)
72#define DAISR_RCNE (1 << 9)
73#define DAISR_LCNF (1 << 10)
74#define DAISR_LCNE (1 << 11)
75#define DAISR_FIFO (1 << 12)
76
77#define SYSCON3_ADCCON (1 << 0)
78#define SYSCON3_DAISEL (1 << 3)
79#define SYSCON3_ADCCKNSEN (1 << 4)
80#define SYSCON3_FASTWAKE (1 << 8)
81#define SYSCON3_DAIEN (1 << 9)
82
83#endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h
deleted file mode 100644
index b442d65c6593..000000000000
--- a/arch/arm/include/asm/hardware/uengine.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Generic library functions for the microengines found on the Intel
3 * IXP2000 series of network processors.
4 *
5 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Dedicated to Marija Kulikova.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU Lesser General Public License as
10 * published by the Free Software Foundation; either version 2.1 of the
11 * License, or (at your option) any later version.
12 */
13
14#ifndef __IXP2000_UENGINE_H
15#define __IXP2000_UENGINE_H
16
17extern u32 ixp2000_uengine_mask;
18
19struct ixp2000_uengine_code
20{
21 u32 cpu_model_bitmask;
22 u8 cpu_min_revision;
23 u8 cpu_max_revision;
24
25 u32 uengine_parameters;
26
27 struct ixp2000_reg_value {
28 int reg;
29 u32 value;
30 } *initial_reg_values;
31
32 int num_insns;
33 u8 *insns;
34};
35
36u32 ixp2000_uengine_csr_read(int uengine, int offset);
37void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
38void ixp2000_uengine_reset(u32 uengine_mask);
39void ixp2000_uengine_set_mode(int uengine, u32 mode);
40void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
41void ixp2000_uengine_init_context(int uengine, int context, int pc);
42void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
43void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
44int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
45
46#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
47#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
48#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
49#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
50#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
51#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
52#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
53#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
54#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
55#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
56#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
57#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
58#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
59#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
60
61
62#endif
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