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authorAlexander Shiyan <shc_work@mail.ru>2012-05-14 13:46:08 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 14:35:37 -0400
commit27723ec4ec7fab52e4e14ec35391390b296cb9d0 (patch)
treea4a237161732f322c4a2c534a301a218220a6d49 /arch/arm/include/asm/hardware
parent94bd32792e905ae25f63491f06d7d3018b350dd2 (diff)
ARM: clps711x: Used own subarch directory for store header file
There is no reason to have the clps7111.h header in a globally visible location, so move it to a place that is only visible when building for mach-clps711x. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r--arch/arm/include/asm/hardware/clps7111.h234
1 files changed, 0 insertions, 234 deletions
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h
deleted file mode 100644
index 0998606920b1..000000000000
--- a/arch/arm/include/asm/hardware/clps7111.h
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/clps7111.h
3 *
4 * This file contains the hardware definitions of the CLPS7111 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_CLPS7111_H
24#define __ASM_HARDWARE_CLPS7111_H
25
26#define CLPS711X_PHYS_BASE (0x80000000)
27
28#define PADR (0x0000)
29#define PBDR (0x0001)
30#define PCDR (0x0002)
31#define PDDR (0x0003)
32#define PADDR (0x0040)
33#define PBDDR (0x0041)
34#define PCDDR (0x0042)
35#define PDDDR (0x0043)
36#define PEDR (0x0080)
37#define PEDDR (0x00c0)
38#define SYSCON1 (0x0100)
39#define SYSFLG1 (0x0140)
40#define MEMCFG1 (0x0180)
41#define MEMCFG2 (0x01c0)
42#define DRFPR (0x0200)
43#define INTSR1 (0x0240)
44#define INTMR1 (0x0280)
45#define LCDCON (0x02c0)
46#define TC1D (0x0300)
47#define TC2D (0x0340)
48#define RTCDR (0x0380)
49#define RTCMR (0x03c0)
50#define PMPCON (0x0400)
51#define CODR (0x0440)
52#define UARTDR1 (0x0480)
53#define UBRLCR1 (0x04c0)
54#define SYNCIO (0x0500)
55#define PALLSW (0x0540)
56#define PALMSW (0x0580)
57#define STFCLR (0x05c0)
58#define BLEOI (0x0600)
59#define MCEOI (0x0640)
60#define TEOI (0x0680)
61#define TC1EOI (0x06c0)
62#define TC2EOI (0x0700)
63#define RTCEOI (0x0740)
64#define UMSEOI (0x0780)
65#define COEOI (0x07c0)
66#define HALT (0x0800)
67#define STDBY (0x0840)
68
69#define FBADDR (0x1000)
70#define SYSCON2 (0x1100)
71#define SYSFLG2 (0x1140)
72#define INTSR2 (0x1240)
73#define INTMR2 (0x1280)
74#define UARTDR2 (0x1480)
75#define UBRLCR2 (0x14c0)
76#define SS2DR (0x1500)
77#define SRXEOF (0x1600)
78#define SS2POP (0x16c0)
79#define KBDEOI (0x1700)
80
81#define DAIR (0x2000)
82#define DAIR0 (0x2040)
83#define DAIDR1 (0x2080)
84#define DAIDR2 (0x20c0)
85#define DAISR (0x2100)
86#define SYSCON3 (0x2200)
87#define INTSR3 (0x2240)
88#define INTMR3 (0x2280)
89#define LEDFLSH (0x22c0)
90#define SDCONF (0x2300)
91#define SDRFPR (0x2340)
92
93/* common bits: SYSCON1 / SYSCON2 */
94#define SYSCON_UARTEN (1 << 8)
95
96#define SYSCON1_KBDSCAN(x) ((x) & 15)
97#define SYSCON1_KBDSCANMASK (15)
98#define SYSCON1_TC1M (1 << 4)
99#define SYSCON1_TC1S (1 << 5)
100#define SYSCON1_TC2M (1 << 6)
101#define SYSCON1_TC2S (1 << 7)
102#define SYSCON1_UART1EN SYSCON_UARTEN
103#define SYSCON1_BZTOG (1 << 9)
104#define SYSCON1_BZMOD (1 << 10)
105#define SYSCON1_DBGEN (1 << 11)
106#define SYSCON1_LCDEN (1 << 12)
107#define SYSCON1_CDENTX (1 << 13)
108#define SYSCON1_CDENRX (1 << 14)
109#define SYSCON1_SIREN (1 << 15)
110#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
111#define SYSCON1_ADCKSEL_MASK (3 << 16)
112#define SYSCON1_EXCKEN (1 << 18)
113#define SYSCON1_WAKEDIS (1 << 19)
114#define SYSCON1_IRTXM (1 << 20)
115
116/* common bits: SYSFLG1 / SYSFLG2 */
117#define SYSFLG_UBUSY (1 << 11)
118#define SYSFLG_URXFE (1 << 22)
119#define SYSFLG_UTXFF (1 << 23)
120
121#define SYSFLG1_MCDR (1 << 0)
122#define SYSFLG1_DCDET (1 << 1)
123#define SYSFLG1_WUDR (1 << 2)
124#define SYSFLG1_WUON (1 << 3)
125#define SYSFLG1_CTS (1 << 8)
126#define SYSFLG1_DSR (1 << 9)
127#define SYSFLG1_DCD (1 << 10)
128#define SYSFLG1_UBUSY SYSFLG_UBUSY
129#define SYSFLG1_NBFLG (1 << 12)
130#define SYSFLG1_RSTFLG (1 << 13)
131#define SYSFLG1_PFFLG (1 << 14)
132#define SYSFLG1_CLDFLG (1 << 15)
133#define SYSFLG1_URXFE SYSFLG_URXFE
134#define SYSFLG1_UTXFF SYSFLG_UTXFF
135#define SYSFLG1_CRXFE (1 << 24)
136#define SYSFLG1_CTXFF (1 << 25)
137#define SYSFLG1_SSIBUSY (1 << 26)
138#define SYSFLG1_ID (1 << 29)
139
140#define SYSFLG2_SSRXOF (1 << 0)
141#define SYSFLG2_RESVAL (1 << 1)
142#define SYSFLG2_RESFRM (1 << 2)
143#define SYSFLG2_SS2RXFE (1 << 3)
144#define SYSFLG2_SS2TXFF (1 << 4)
145#define SYSFLG2_SS2TXUF (1 << 5)
146#define SYSFLG2_CKMODE (1 << 6)
147#define SYSFLG2_UBUSY SYSFLG_UBUSY
148#define SYSFLG2_URXFE SYSFLG_URXFE
149#define SYSFLG2_UTXFF SYSFLG_UTXFF
150
151#define LCDCON_GSEN (1 << 30)
152#define LCDCON_GSMD (1 << 31)
153
154#define SYSCON2_SERSEL (1 << 0)
155#define SYSCON2_KBD6 (1 << 1)
156#define SYSCON2_DRAMZ (1 << 2)
157#define SYSCON2_KBWEN (1 << 3)
158#define SYSCON2_SS2TXEN (1 << 4)
159#define SYSCON2_PCCARD1 (1 << 5)
160#define SYSCON2_PCCARD2 (1 << 6)
161#define SYSCON2_SS2RXEN (1 << 7)
162#define SYSCON2_UART2EN SYSCON_UARTEN
163#define SYSCON2_SS2MAEN (1 << 9)
164#define SYSCON2_OSTB (1 << 12)
165#define SYSCON2_CLKENSL (1 << 13)
166#define SYSCON2_BUZFREQ (1 << 14)
167
168/* common bits: UARTDR1 / UARTDR2 */
169#define UARTDR_FRMERR (1 << 8)
170#define UARTDR_PARERR (1 << 9)
171#define UARTDR_OVERR (1 << 10)
172
173/* common bits: UBRLCR1 / UBRLCR2 */
174#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
175#define UBRLCR_BREAK (1 << 12)
176#define UBRLCR_PRTEN (1 << 13)
177#define UBRLCR_EVENPRT (1 << 14)
178#define UBRLCR_XSTOP (1 << 15)
179#define UBRLCR_FIFOEN (1 << 16)
180#define UBRLCR_WRDLEN5 (0 << 17)
181#define UBRLCR_WRDLEN6 (1 << 17)
182#define UBRLCR_WRDLEN7 (2 << 17)
183#define UBRLCR_WRDLEN8 (3 << 17)
184#define UBRLCR_WRDLEN_MASK (3 << 17)
185
186#define SYNCIO_SMCKEN (1 << 13)
187#define SYNCIO_TXFRMEN (1 << 14)
188
189#define DAIR_DAIEN (1 << 16)
190#define DAIR_ECS (1 << 17)
191#define DAIR_LCTM (1 << 19)
192#define DAIR_LCRM (1 << 20)
193#define DAIR_RCTM (1 << 21)
194#define DAIR_RCRM (1 << 22)
195#define DAIR_LBM (1 << 23)
196
197#define DAIDR2_FIFOEN (1 << 15)
198#define DAIDR2_FIFOLEFT (0x0d << 16)
199#define DAIDR2_FIFORIGHT (0x11 << 16)
200
201#define DAISR_RCTS (1 << 0)
202#define DAISR_RCRS (1 << 1)
203#define DAISR_LCTS (1 << 2)
204#define DAISR_LCRS (1 << 3)
205#define DAISR_RCTU (1 << 4)
206#define DAISR_RCRO (1 << 5)
207#define DAISR_LCTU (1 << 6)
208#define DAISR_LCRO (1 << 7)
209#define DAISR_RCNF (1 << 8)
210#define DAISR_RCNE (1 << 9)
211#define DAISR_LCNF (1 << 10)
212#define DAISR_LCNE (1 << 11)
213#define DAISR_FIFO (1 << 12)
214
215#define SYSCON3_ADCCON (1 << 0)
216#define SYSCON3_DAISEL (1 << 3)
217#define SYSCON3_ADCCKNSEN (1 << 4)
218#define SYSCON3_FASTWAKE (1 << 8)
219#define SYSCON3_DAIEN (1 << 9)
220
221#define SDCONF_ACTIVE (1 << 10)
222#define SDCONF_CLKCTL (1 << 9)
223#define SDCONF_WIDTH_4 (0 << 7)
224#define SDCONF_WIDTH_8 (1 << 7)
225#define SDCONF_WIDTH_16 (2 << 7)
226#define SDCONF_WIDTH_32 (3 << 7)
227#define SDCONF_SIZE_16 (0 << 5)
228#define SDCONF_SIZE_64 (1 << 5)
229#define SDCONF_SIZE_128 (2 << 5)
230#define SDCONF_SIZE_256 (3 << 5)
231#define SDCONF_CASLAT_2 (2)
232#define SDCONF_CASLAT_3 (3)
233
234#endif /* __ASM_HARDWARE_CLPS7111_H */
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