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authorGrant Likely <grant.likely@secretlab.ca>2012-03-12 11:41:28 -0400
committerGrant Likely <grant.likely@secretlab.ca>2012-03-12 11:41:28 -0400
commite2aa4177264c1a459779d6e35fae22adf17a9232 (patch)
treebeba4b40aa90f6f033eb261cf5a5453c5957c87c /arch/arm/common/it8152.c
parent25db711df3258d125dc1209800317e5c0ef3c870 (diff)
parentfde7d9049e55ab85a390be7f415d74c9f62dd0f9 (diff)
Merge tag 'v3.3-rc7' into gpio/next
Linux 3.3-rc7. Merged into the gpio branch to pick up gpio bugfixes already in mainline before queueing up move v3.4 patches
Diffstat (limited to 'arch/arm/common/it8152.c')
-rw-r--r--arch/arm/common/it8152.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13ebc..fb1f1cfce60c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
320 return -EBUSY; 320 return -EBUSY;
321} 321}
322 322
323/*
324 * If we set up a device for bus mastering, we need to check the latency
325 * timer as we don't have even crappy BIOSes to set it properly.
326 * The implementation is from arch/i386/pci/i386.c
327 */
328unsigned int pcibios_max_latency = 255;
329
330/* ITE bridge requires setting latency timer to avoid early bus access 323/* ITE bridge requires setting latency timer to avoid early bus access
331 termination by PCI bus master devices 324 termination by PCI bus master devices
332*/ 325*/