diff options
| author | Fugang Duan <B38611@freescale.com> | 2014-02-14 23:30:59 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:31 -0400 |
| commit | d41271fb6f186d6d727c0bf08832b6b8154fbdda (patch) | |
| tree | bcc0f68a212ea8ad2f8ea9214aa2e79d183ef224 /arch/arm/boot | |
| parent | 8452fe0f4eea62b3172726974c91006ae1d02a5e (diff) | |
ENGR00299323-12 ARM: dts: imx6sx: add fec nodes and iomux pin group
- Add enet1 and enet2 nodes.
- Add enet iomux pin group for enet1 and enet2.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index d76c9e9a0811..819e463a5124 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi | |||
| @@ -229,6 +229,26 @@ | |||
| 229 | reg = <0x0217c000 0x4000>; | 229 | reg = <0x0217c000 0x4000>; |
| 230 | }; | 230 | }; |
| 231 | 231 | ||
| 232 | fec1: ethernet@02188000 { | ||
| 233 | compatible = "fsl,imx6sx-fec"; | ||
| 234 | reg = <0x02188000 0x4000>; | ||
| 235 | interrupts = <0 118 0x04 0 119 0x04>; | ||
| 236 | clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>, | ||
| 237 | <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET_REF>; | ||
| 238 | clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; | ||
| 239 | status = "disabled"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | fec2: ethernet@021b4000 { | ||
| 243 | compatible = "fsl,imx6sx-fec"; | ||
| 244 | reg = <0x021b4000 0x4000>; | ||
| 245 | interrupts = <0 102 0x04 0 103 0x04>; | ||
| 246 | clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>, | ||
| 247 | <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET2_REF_125M>; | ||
| 248 | clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; | ||
| 249 | status = "disabled"; | ||
| 250 | }; | ||
| 251 | |||
| 232 | usdhc3: usdhc@02198000 { | 252 | usdhc3: usdhc@02198000 { |
| 233 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | 253 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 234 | reg = <0x02198000 0x4000>; | 254 | reg = <0x02198000 0x4000>; |
| @@ -293,6 +313,46 @@ | |||
| 293 | }; | 313 | }; |
| 294 | 314 | ||
| 295 | &iomuxc { | 315 | &iomuxc { |
| 316 | enet1 { | ||
| 317 | pinctrl_enet1_1: enet1grp-1 { | ||
| 318 | fsl,pins = < | ||
| 319 | MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 | ||
| 320 | MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 | ||
| 321 | MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 | ||
| 322 | MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 | ||
| 323 | MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 | ||
| 324 | MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 | ||
| 325 | MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 | ||
| 326 | MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 | ||
| 327 | MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 | ||
| 328 | MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 | ||
| 329 | MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 | ||
| 330 | MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 | ||
| 331 | MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 | ||
| 332 | MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 | ||
| 333 | >; | ||
| 334 | }; | ||
| 335 | }; | ||
| 336 | |||
| 337 | enet2 { | ||
| 338 | pinctrl_enet2_1: enet2grp-1 { | ||
| 339 | fsl,pins = < | ||
| 340 | MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b1 | ||
| 341 | MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 | ||
| 342 | MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b0 | ||
| 343 | MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b0 | ||
| 344 | MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b0 | ||
| 345 | MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b0 | ||
| 346 | MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 | ||
| 347 | MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 | ||
| 348 | MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 | ||
| 349 | MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 | ||
| 350 | MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 | ||
| 351 | MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 | ||
| 352 | >; | ||
| 353 | }; | ||
| 354 | }; | ||
| 355 | |||
| 296 | uart1 { | 356 | uart1 { |
| 297 | pinctrl_uart1_1: uart1grp-1 { | 357 | pinctrl_uart1_1: uart1grp-1 { |
| 298 | fsl,pins = < | 358 | fsl,pins = < |