diff options
author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-03-25 23:11:25 -0400 |
---|---|---|
committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:58:10 -0400 |
commit | d27f37e52d922958ffaf98a348fa11bde7bc6664 (patch) | |
tree | 4007e6fd4ebc96cc5d6a128ab01ca82f630a62c3 /arch/arm/boot | |
parent | 4e815f70656fa769ce08a3b0e307f1705415220d (diff) |
ENGR00305648-3 ARM: imx6sx: Add audio nodes to dtsi
This patch adds SPDIF SAI ASRC_P2P and ESAI support to imx6sx.dtsi
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 519e1ea5fa9b..73488a3223f1 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi | |||
@@ -220,6 +220,40 @@ | |||
220 | status = "disabled"; | 220 | status = "disabled"; |
221 | }; | 221 | }; |
222 | 222 | ||
223 | spdif: spdif@02004000 { | ||
224 | compatible = "fsl,imx6sx-spdif", | ||
225 | "fsl,imx35-spdif"; | ||
226 | reg = <0x02004000 0x4000>; | ||
227 | interrupts = <0 52 0x04>; | ||
228 | dmas = <&sdma 14 18 0>, | ||
229 | <&sdma 15 18 0>; | ||
230 | dma-names = "rx", "tx"; | ||
231 | clocks = <&clks IMX6SX_CLK_SPDIF>, | ||
232 | <&clks IMX6SX_CLK_OSC>, | ||
233 | <&clks IMX6SX_CLK_SPDIF>, | ||
234 | <&clks 0>, <&clks 0>, <&clks 0>, | ||
235 | <&clks IMX6SX_CLK_IPG>, | ||
236 | <&clks 0>, <&clks 0>, | ||
237 | <&clks IMX6SX_CLK_SPBA>; | ||
238 | clock-names = "core", "rxtx0", | ||
239 | "rxtx1", "rxtx2", | ||
240 | "rxtx3", "rxtx4", | ||
241 | "rxtx5", "rxtx6", | ||
242 | "rxtx7", "dma"; | ||
243 | status = "disabled"; | ||
244 | }; | ||
245 | |||
246 | esai: esai@02024000 { | ||
247 | compatible = "fsl,imx6q-esai"; | ||
248 | reg = <0x02024000 0x4000>; | ||
249 | interrupts = <0 51 0x04>; | ||
250 | clocks = <&clks IMX6SX_CLK_ESAI>, <&clks IMX6SX_CLK_SPBA>; | ||
251 | clock-names = "core", "dma"; | ||
252 | fsl,esai-dma-events = <24 23>; | ||
253 | fsl,flags = <1>; | ||
254 | status = "disabled"; | ||
255 | }; | ||
256 | |||
223 | asrc: asrc@02034000 { | 257 | asrc: asrc@02034000 { |
224 | compatible = "fsl,imx53-asrc"; | 258 | compatible = "fsl,imx53-asrc"; |
225 | reg = <0x02034000 0x4000>; | 259 | reg = <0x02034000 0x4000>; |
@@ -236,6 +270,15 @@ | |||
236 | status = "okay"; | 270 | status = "okay"; |
237 | }; | 271 | }; |
238 | 272 | ||
273 | asrc_p2p: asrc_p2p { | ||
274 | compatible = "fsl,imx6q-asrc-p2p"; | ||
275 | fsl,output-rate = <48000>; | ||
276 | fsl,output-width = <16>; | ||
277 | fsl,asrc-dma-rx-events = <17 18 19>; | ||
278 | fsl,asrc-dma-tx-events = <20 21 22>; | ||
279 | status = "okay"; | ||
280 | }; | ||
281 | |||
239 | ssi1: ssi@02028000 { | 282 | ssi1: ssi@02028000 { |
240 | compatible = "fsl,imx6sx-ssi","fsl,imx21-ssi"; | 283 | compatible = "fsl,imx6sx-ssi","fsl,imx21-ssi"; |
241 | reg = <0x02028000 0x4000>; | 284 | reg = <0x02028000 0x4000>; |
@@ -660,6 +703,30 @@ | |||
660 | status = "disabled"; | 703 | status = "disabled"; |
661 | }; | 704 | }; |
662 | 705 | ||
706 | sai1: sai@021d4000 { | ||
707 | compatible = "fsl,imx6sx-sai"; | ||
708 | reg = <0x021d4000 0x4000>; | ||
709 | interrupts = <0 97 0x04>; | ||
710 | clocks = <&clks IMX6SX_CLK_SAI1_IPG>, <&clks IMX6SX_CLK_SAI1>; | ||
711 | clock-names = "ipg", "sai"; | ||
712 | dma-names = "rx", "tx"; | ||
713 | dmas = <&sdma 31 23 0>, <&sdma 32 23 0>; | ||
714 | dma-source = <&gpr 0 15 0 16>; | ||
715 | status = "disabled"; | ||
716 | }; | ||
717 | |||
718 | sai2: sai@021dc000 { | ||
719 | compatible = "fsl,imx6sx-sai"; | ||
720 | reg = <0x021dc000 0x4000>; | ||
721 | interrupts = <0 98 0x04>; | ||
722 | clocks = <&clks IMX6SX_CLK_SAI2_IPG>, <&clks IMX6SX_CLK_SAI2>; | ||
723 | clock-names = "ipg", "sai"; | ||
724 | dma-names = "rx", "tx"; | ||
725 | dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; | ||
726 | dma-source = <&gpr 0 17 0 18>; | ||
727 | status = "disabled"; | ||
728 | }; | ||
729 | |||
663 | fec1: ethernet@02188000 { | 730 | fec1: ethernet@02188000 { |
664 | compatible = "fsl,imx6sx-fec"; | 731 | compatible = "fsl,imx6sx-fec"; |
665 | reg = <0x02188000 0x4000>; | 732 | reg = <0x02188000 0x4000>; |
@@ -1141,6 +1208,24 @@ | |||
1141 | }; | 1208 | }; |
1142 | }; | 1209 | }; |
1143 | 1210 | ||
1211 | esai { | ||
1212 | pinctrl_esai_1: esaigrp-1 { | ||
1213 | fsl,pins = < | ||
1214 | MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 | ||
1215 | MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 | ||
1216 | MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 | ||
1217 | MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 | ||
1218 | MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 | ||
1219 | MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 | ||
1220 | MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 | ||
1221 | MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 | ||
1222 | MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 | ||
1223 | MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 | ||
1224 | MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 | ||
1225 | >; | ||
1226 | }; | ||
1227 | }; | ||
1228 | |||
1144 | flexcan1 { | 1229 | flexcan1 { |
1145 | pinctrl_flexcan1_1: flexcan1grp-1 { | 1230 | pinctrl_flexcan1_1: flexcan1grp-1 { |
1146 | fsl,pins = < | 1231 | fsl,pins = < |
@@ -1330,6 +1415,28 @@ | |||
1330 | }; | 1415 | }; |
1331 | }; | 1416 | }; |
1332 | 1417 | ||
1418 | sai1 { | ||
1419 | pinctrl_sai1_1: sai1grp_1 { | ||
1420 | fsl,pins = < | ||
1421 | MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 | ||
1422 | MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 | ||
1423 | MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 | ||
1424 | MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 | ||
1425 | MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 | ||
1426 | MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 | ||
1427 | >; | ||
1428 | }; | ||
1429 | }; | ||
1430 | |||
1431 | spdif { | ||
1432 | pinctrl_spdif_1: spdifgrp-1 { | ||
1433 | fsl,pins = < | ||
1434 | MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 | ||
1435 | MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 | ||
1436 | >; | ||
1437 | }; | ||
1438 | }; | ||
1439 | |||
1333 | uart1 { | 1440 | uart1 { |
1334 | pinctrl_uart1_1: uart1grp-1 { | 1441 | pinctrl_uart1_1: uart1grp-1 { |
1335 | fsl,pins = < | 1442 | fsl,pins = < |