ENGR00313685-10 of/irq: Fix bug in interrupt parsing refactor.

commit 78119fd1068cc068f6112a57a5f6de0e5b20245a upstream.

Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced
a bug. The irq parsing will fail for some nodes that don't have a reg
property. It is fixed by deferring the check for reg until it is
actually needed. Also adjust the testcase data to catch the bug.

Signed-off-by: Grant Likely <grant.likely@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Ming Lei <tom.leiming@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 4 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
index 560d6bf680b6..c843720bd3e5 100644
--- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
+++ b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
@@ -2,7 +2,8 @@
 / {
         testcase-data {
                 interrupts {
-                        #address-cells = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
                         test_intc0: intc0 {
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
@@ -29,8 +30,7 @@
 
                         test_intmap1: intmap1 {
                                 #interrupt-cells = <2>;
-                                #address-cells = <0>;
-                                interrupt-map = <1 2 &test_intc0 15>;
+                                interrupt-map = <0x5000 1 2 &test_intc0 15>;
                         };
 
                         interrupts0 {
@@ -44,6 +44,7 @@
                         };
 
                         interrupts-extended0 {
+                                reg = <0x5000 0x100>;
                                 interrupts-extended = <&test_intc0 1>,
                                                       <&test_intc1 2 3 4>,
                                                       <&test_intc2 5 6>,