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authorAllen Xu <b45815@freescale.com>2014-07-14 18:02:22 -0400
committerAllen Xu <b45815@freescale.com>2014-07-21 14:49:22 -0400
commit77543e2c1d8f5e891796c5278d0143679808ea03 (patch)
tree16573142e8e37ec237ea4ae98542b3dfd98d80d4 /arch/arm/boot
parent50ef3db3e4c83bc7b0da05c1dac1af88328d73f4 (diff)
ENGR00323464 ARM: dts: imx6sx: add gpmi-weim dts file
Add new dts file and enable gpmi module. Signed-off-by: Allen Xu <b45815@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts534
2 files changed, 535 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index efc8bb828ae5..0aa0a95e00d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -139,6 +139,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
139 imx6sl-evk-ldo.dtb \ 139 imx6sl-evk-ldo.dtb \
140 imx6sl-evk-pf200.dtb \ 140 imx6sl-evk-pf200.dtb \
141 imx6sx-17x17-arm2.dtb \ 141 imx6sx-17x17-arm2.dtb \
142 imx6sx-17x17-arm2-gpmi-weim.dtb \
142 imx6sx-17x17-arm2-sai.dtb \ 143 imx6sx-17x17-arm2-sai.dtb \
143 imx6sx-17x17-arm2-ssi.dtb \ 144 imx6sx-17x17-arm2-ssi.dtb \
144 imx6sx-17x17-arm2-spdif.dtb \ 145 imx6sx-17x17-arm2-spdif.dtb \
diff --git a/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
new file mode 100644
index 000000000000..13b62024f8eb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
@@ -0,0 +1,534 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sx.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloX 17x17 ARM2 Board";
15 compatible = "fsl,imx6sx-17x17-arm2", "fsl,imx6sx";
16
17 backlight {
18 compatible = "pwm-backlight";
19 pwms = <&pwm3 0 5000000>;
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
22 };
23
24 clocks {
25 codec_osc: codec_osc {
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <12000000>;
29 };
30 };
31
32 max7322_reset: max7322-reset {
33 compatible = "gpio-reset";
34 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
35 reset-delay-us = <1>;
36 #reset-cells = <0>;
37 };
38
39 pxp_v4l2_out {
40 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
41 status = "okay";
42 };
43
44 regulators {
45 compatible = "simple-bus";
46
47 reg_3p3v: 3p3v {
48 compatible = "regulator-fixed";
49 regulator-name = "3P3V";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-always-on;
53 };
54
55 reg_sdb_vmmc: sdb_vmmc{
56 compatible = "regulator-fixed";
57 regulator-name = "SD2_SPWR";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
61 };
62
63 reg_usb_otg1_vbus: usb_otg1_vbus {
64 compatible = "regulator-fixed";
65 regulator-name = "usb_otg1_vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 gpio = <&gpio1 9 0>;
69 enable-active-high;
70 };
71
72 reg_usb_otg2_vbus: usb_otg2_vbus {
73 compatible = "regulator-fixed";
74 regulator-name = "usb_otg2_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 12 0>;
78 enable-active-high;
79 };
80
81 reg_vref_3v3: regulator@0 {
82 compatible = "regulator-fixed";
83 regulator-name = "vref-3v3";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 };
87 };
88
89 memory {
90 reg = <0x80000000 0x40000000>;
91 };
92
93 sound {
94 compatible = "fsl,imx6sx-arm2-sgtl5000",
95 "fsl,imx-audio-sgtl5000";
96 model = "imx6sx-arm2-sgtl5000";
97 cpu-dai = <&ssi1>;
98 audio-codec = <&codec>;
99 audio-routing =
100 "LINE_IN", "Line In Jack",
101 "Headphone Jack", "HP_OUT";
102 mux-int-port = <1>;
103 mux-ext-port = <4>;
104 };
105};
106
107&adc1 {
108 vref-supply = <&reg_vref_3v3>;
109 status = "okay";
110};
111
112&adc2 {
113 vref-supply = <&reg_vref_3v3>;
114 status = "okay";
115};
116
117&audmux {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_audmux_2>;
120 status = "okay";
121};
122
123&ecspi4 {
124 fsl,spi-num-chipselects = <1>;
125 cs-gpios = <&gpio7 4 0>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
128 status = "disabled"; /* pin conflict with USDHC3 */
129
130 flash: m25p80@0 {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "st,m25p32";
134 spi-max-frequency = <20000000>;
135 reg = <0>;
136 };
137};
138
139&fec1 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_enet1_1>;
142 phy-mode = "rgmii";
143 phy-id = <1>;
144 fsl,num_tx_queues=<3>;
145 fsl,num_rx_queues=<3>;
146 pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
147 fsl,magic-packet;
148 status = "okay";
149};
150
151&fec2 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_enet2_1>;
154 phy-mode = "rgmii";
155 phy-id = <0>;
156 fsl,num_tx_queues=<3>;
157 fsl,num_rx_queues=<3>;
158 pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
159 fsl,magic-packet;
160 status = "okay";
161};
162
163&flexcan1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_flexcan1_1>;
166 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
167 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
168 trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
169 status = "okay";
170};
171
172&flexcan2 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexcan2_1>;
175 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
176 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
177 trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
178 status = "okay";
179};
180
181&gpc {
182 fsl,cpu_pupscr_sw2iso = <0xf>;
183 fsl,cpu_pupscr_sw = <0xf>;
184 fsl,cpu_pdnscr_iso2sw = <0x1>;
185 fsl,cpu_pdnscr_iso = <0x1>;
186 fsl,wdog-reset = <1>; /* watchdog select of reset source */
187};
188
189&gpmi {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
192 status = "okay"; /* pin conflict with qspi*/
193};
194
195&i2c1 {
196 clock-frequency = <100000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_i2c1_1>;
199 status = "okay";
200
201 pmic: pfuze100@08 {
202 compatible = "fsl,pfuze100";
203 reg = <0x08>;
204
205 regulators {
206 sw1a_reg: sw1ab {
207 regulator-min-microvolt = <300000>;
208 regulator-max-microvolt = <1875000>;
209 regulator-boot-on;
210 regulator-always-on;
211 regulator-ramp-delay = <6250>;
212 };
213
214 sw1c_reg: sw1c {
215 regulator-min-microvolt = <300000>;
216 regulator-max-microvolt = <1875000>;
217 regulator-boot-on;
218 regulator-always-on;
219 regulator-ramp-delay = <6250>;
220 };
221
222 sw2_reg: sw2 {
223 regulator-min-microvolt = <800000>;
224 regulator-max-microvolt = <3300000>;
225 regulator-boot-on;
226 regulator-always-on;
227 };
228
229 sw3a_reg: sw3a {
230 regulator-min-microvolt = <400000>;
231 regulator-max-microvolt = <1975000>;
232 regulator-boot-on;
233 regulator-always-on;
234 };
235
236 sw3b_reg: sw3b {
237 regulator-min-microvolt = <400000>;
238 regulator-max-microvolt = <1975000>;
239 regulator-boot-on;
240 regulator-always-on;
241 };
242
243 sw4_reg: sw4 {
244 regulator-min-microvolt = <800000>;
245 regulator-max-microvolt = <3300000>;
246 };
247
248 swbst_reg: swbst {
249 regulator-min-microvolt = <5000000>;
250 regulator-max-microvolt = <5150000>;
251 };
252
253 snvs_reg: vsnvs {
254 regulator-min-microvolt = <1000000>;
255 regulator-max-microvolt = <3000000>;
256 regulator-boot-on;
257 regulator-always-on;
258 };
259
260 vref_reg: vrefddr {
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 vgen1_reg: vgen1 {
266 regulator-min-microvolt = <800000>;
267 regulator-max-microvolt = <1550000>;
268 };
269
270 vgen2_reg: vgen2 {
271 regulator-min-microvolt = <800000>;
272 regulator-max-microvolt = <1550000>;
273 };
274
275 vgen3_reg: vgen3 {
276 regulator-min-microvolt = <1800000>;
277 regulator-max-microvolt = <3300000>;
278 regulator-always-on;
279 };
280
281 vgen4_reg: vgen4 {
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <3300000>;
284 regulator-always-on;
285 };
286
287 vgen5_reg: vgen5 {
288 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <3300000>;
290 regulator-always-on;
291 };
292
293 vgen6_reg: vgen6 {
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <3300000>;
296 regulator-always-on;
297 };
298 };
299 };
300};
301
302&i2c2 {
303 clock-frequency = <100000>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_i2c2_1>;
306 status = "okay";
307
308 max7322_1: gpio@68 {
309 compatible = "maxim,max7322";
310 reg = <0x68>;
311 gpio-controller;
312 #gpio-cells = <2>;
313 resets = <&max7322_reset>;
314 };
315
316 max7322_2: gpio@69 {
317 compatible = "maxim,max7322";
318 reg = <0x69>;
319 gpio-controller;
320 #gpio-cells = <2>;
321 resets = <&max7322_reset>;
322 };
323
324 codec: sgtl5000@0a {
325 compatible = "fsl,sgtl5000";
326 reg = <0x0a>;
327 clocks = <&codec_osc>;
328 VDDA-supply = <&vgen4_reg>;
329 VDDIO-supply = <&reg_3p3v>;
330 };
331};
332
333
334&i2c3 {
335 clock-frequency = <100000>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c3_1>;
338 status = "okay";
339};
340
341&i2c4 {
342 clock-frequency = <100000>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_i2c4_1>;
345 status = "okay";
346};
347
348&iomuxc {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_hog_1>;
351
352 hog {
353 pinctrl_hog_1: hoggrp-1 {
354 fsl,pins = <
355 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059
356 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059
357 MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
358 /* CAN1_2_EN */
359 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
360 /* CAN1_2_STBY_B */
361 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
362 /* CAN1_ERR_B */
363 MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
364 /* CAN2_ERR_B */
365 MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
366 /* SD2_PWROFF */
367 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
368 >;
369 };
370 };
371};
372
373&lcdif1 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_lcdif_dat_0
376 &pinctrl_lcdif_ctrl_0>;
377 display = <&display>;
378 status = "okay";
379
380 display: display {
381 bits-per-pixel = <16>;
382 bus-width = <24>;
383
384 display-timings {
385 native-mode = <&timing0>;
386 timing0: timing0 {
387 clock-frequency = <33500000>;
388 hactive = <800>;
389 vactive = <480>;
390 hback-porch = <89>;
391 hfront-porch = <164>;
392 vback-porch = <23>;
393 vfront-porch = <10>;
394 hsync-len = <10>;
395 vsync-len = <10>;
396 hsync-active = <0>;
397 vsync-active = <0>;
398 de-active = <1>;
399 pixelclk-active = <0>;
400 };
401 };
402 };
403};
404
405&mlb {
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_mlb_1>;
408 status = "disabled";/* pin conflict with usdhc2*/
409};
410
411&pwm3 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_pwm3_0>;
414 status = "okay";
415};
416
417&pxp {
418 status = "okay";
419};
420
421&qspi2 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_qspi2_1>;
424 status = "disabled";
425
426 flash0: n25q256a@0 {
427 #address-cells = <1>;
428 #size-cells = <1>;
429 compatible = "micron,n25q256a";
430 spi-max-frequency = <53000000>;
431 reg = <0>;
432 };
433
434 flash1: n25q256a@1 {
435 #address-cells = <1>;
436 #size-cells = <1>;
437 compatible = "micron,n25q256a";
438 spi-max-frequency = <53000000>;
439 reg = <1>;
440 };
441};
442
443&sai2 {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_sai2_1>;
446 status = "disabled";
447};
448
449&spdif {
450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_spdif_1>;
452 status = "disabled";
453};
454
455&ssi1 {
456 fsl,mode = "i2s-slave";
457 status = "okay";
458};
459
460&uart1 {
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_uart1_1>;
463 status = "okay";
464};
465
466&uart2 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_uart2_1>;
469 status = "okay";
470};
471
472&usbh {
473 pinctrl-names = "idle", "active";
474 pinctrl-0 = <&pinctrl_usbh_1>;
475 pinctrl-1 = <&pinctrl_usbh_2>;
476 osc-clkgate-delay = <0x3>;
477 pad-supply = <&vgen1_reg>;
478 status = "okay";
479};
480
481&usbotg1 {
482 vbus-supply = <&reg_usb_otg1_vbus>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_usbotg1_1>;
485 disable-over-current;
486 status = "okay";
487};
488
489&usbotg2 {
490 /*
491 * Pin conflict with others, need to switch R580 & R579
492 * to B and disable pwm3 to enable it.
493 */
494 vbus-supply = <&reg_usb_otg2_vbus>;
495 disable-over-current;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_usbotg2_1>;
498 status = "disabled";
499};
500
501&usdhc2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_usdhc2_1>;
504 non-removable;
505 /* need hw rework to enable signal voltage switch */
506 no-1-8-v;
507 keep-power-in-suspend;
508 enable-sdio-wakeup;
509 status = "okay";
510};
511
512&usdhc3 {
513 pinctrl-names = "default", "state_100mhz", "state_200mhz";
514 pinctrl-0 = <&pinctrl_usdhc3_1>;
515 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
516 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
517 bus-width = <8>;
518 cd-gpios = <&gpio2 10 0>;
519 wp-gpios = <&gpio2 15 0>;
520 keep-power-in-suspend;
521 enable-sdio-wakeup;
522 vmmc-supply = <&reg_sdb_vmmc>;
523 status = "okay";
524};
525
526&usdhc4 {
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_usdhc4_1>;
529 bus-width = <8>;
530 non-removable;
531 /* need hw rework to enable signal voltage switch */
532 no-1-8-v;
533 status = "okay";
534};
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