ENGR00318063-2: ARM: imx6q: fix axi_sels mux setting

The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one.  Fix it to match the clock tree in Reference Manual,
and update busfreq driver regarding parent switching on that.  Note,
the parent checking before calling clk_set_parent() in busfreq driver
isn't really necessary, because clk API will make the check and do
nothing if the new parent is the same one as the old.

One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy axi_alt_sel only when axi_sel selects the other
path, i.e. periph.  Otherwise, a glitch could be generated on
axi_alt_sel and get propagated into the divider axi_podf.  In that case,
axi_podf gets locked up and axi clock has no output.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index e2bedf6d8917..511a1544a60d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -56,9 +56,9 @@
                 busfreq { /* BUSFREQ */
                         compatible = "fsl,imx6_busfreq";
                         clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
-                                <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
+                                <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 230>, <&clks 22> , <&clks 8>;
                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
-                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
+                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
                         interrupts = <0 107 0x04>, <0 112 0x4>;
                         interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
                         fsl,max_ddr_freq = <400000000>;