ENGR00300430-9 ARM: dts: imx6sx: add the properties for QuadSpi

add the qspi2 property and its pinctrl.

Signed-off-by: Huang Shijie <b32955@freescale.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 040ca9f71ddc..2eaa9059414a 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -458,6 +458,19 @@
                                 reg = <0x021b0000 0x4000>;
                         };
 
+                        qspi2: qspi@021e4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sx-qspi";
+                                reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
+                                reg-names = "QuadSPI", "QuadSPI-memory";
+                                interrupts = <0 109 0x04>;
+                                clocks = <&clks IMX6SX_CLK_QSPI2>,
+                                        <&clks IMX6SX_CLK_QSPI2>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+
                         romcp@021ac000 {
                                 compatible = "fsl,imx6sx-romcp", "syscon";
                                 reg = <0x021ac000 0x4000>;
@@ -708,6 +721,25 @@
                 };
         };
 
+        qspi2 {
+                pinctrl_qspi2_1: qspi2grp_1 {
+                        fsl,pins = <
+                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
+                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
+                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
+                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
+                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
+                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
+                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
+                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
+                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
+                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
+                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
+                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
+                        >;
+                };
+        };
+
         uart1 {
                 pinctrl_uart1_1: uart1grp-1 {
                         fsl,pins = <