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authorLoren HUANG <b02279@freescale.com>2014-02-26 06:01:05 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:58:04 -0400
commit295b25c9c8ad8def7be18b1630325e5b887cbf44 (patch)
tree38f779cda00c7bdf862b56d216ecc4568bf46eab /arch/arm/boot
parent2da2e5b4425e79da040e941c8d96597c24fd2e02 (diff)
ENGR00303542-3 dts:Add gpu description into imx6sx dtsi
-Add gpu description into imx6sx dtsi to enable gc400t. Signed-off-by: Loren HUANG <b02279@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 73285aa81334..e33500a9dfdb 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -110,6 +110,21 @@
110 arm,data-latency = <4 2 3>; 110 arm,data-latency = <4 2 3>;
111 }; 111 };
112 112
113 gpu: gpu@01800000 {
114 compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
115 reg = <0x01800000 0x4000>, <0x80000000 0x0>;
116 reg-names = "iobase_3d", "phys_baseaddr";
117 interrupts = <0 10 0x04>;
118 interrupt-names = "irq_3d";
119 clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
120 <&clks 0>;
121 clock-names = "gpu3d_axi_clk", "gpu3d_clk",
122 "gpu3d_shader_clk";
123 resets = <&src 0>;
124 reset-names = "gpu3d";
125 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
126 };
127
113 aips-bus@02000000 { /* AIPS1 */ 128 aips-bus@02000000 { /* AIPS1 */
114 compatible = "fsl,aips-bus", "simple-bus"; 129 compatible = "fsl,aips-bus", "simple-bus";
115 #address-cells = <1>; 130 #address-cells = <1>;