ARM: zynq: dts: split up device tree

The purpose of the created zynq-7000.dtsi file is to describe the
hardware common to all Zynq 7000-based boards.  Also, get rid of the
zynq-ep107 device tree, since it is not hardware anyone can purchase.

Add a zc702 dts file based on the zynq-7000.dtsi.  Add it to the
dts/Makefile so it is built with the 'dtbs' target.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 0 insertions, 70 deletions

diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
deleted file mode 100644
index 5caf10011f59..000000000000
--- a/arch/arm/boot/dts/zynq-ep107.dts
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-/ {
-        model = "Xilinx Zynq EP107";
-        compatible = "xlnx,zynq-ep107";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-
-        memory {
-                device_type = "memory";
-                reg = <0x0 0x10000000>;
-        };
-
-        chosen {
-                bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
-                linux,stdout-path = &uart0;
-        };
-
-        amba {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                intc: interrupt-controller@f8f01000 {
-                        compatible = "arm,cortex-a9-gic";
-                        #interrupt-cells = <3>;
-                        #address-cells = <1>;
-                        interrupt-controller;
-                        reg = <0xF8F01000 0x1000>,
-                              <0xF8F00100 0x100>;
-                };
-
-                L2: cache-controller {
-                        compatible = "arm,pl310-cache";
-                        reg = <0xF8F02000 0x1000>;
-                        arm,data-latency = <2 3 2>;
-                        arm,tag-latency = <2 3 2>;
-                        cache-unified;
-                        cache-level = <2>;
-                };
-
-                uart0: uart@e0000000 {
-                        compatible = "xlnx,xuartps";
-                        reg = <0xE0000000 0x1000>;
-                        interrupts = <0 27 4>;
-                        clock = <50000000>;
-                };
-
-                uart1: uart@e0001000 {
-                        compatible = "xlnx,xuartps";
-                        reg = <0xE0001000 0x1000>;
-                        interrupts = <0 50 4>;
-                        clock = <50000000>;
-                };
-        };
-};