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authorMark Zhang <markz@nvidia.com>2012-10-25 02:52:30 -0400
committerStephen Warren <swarren@nvidia.com>2012-11-15 17:07:28 -0500
commitcf63346401c61d7910263d2537bb2d8d265156fa (patch)
treec2b00239942772ca426207d8b186803dbf6cd037 /arch/arm/boot/dts/tegra20-ventana.dts
parent6fb11131ef3400364381661186a55a73b782c3be (diff)
ARM: dt: tegra: ventana: define pinmux for ddc
Tegra 2's I2C2 controller can be routed to either the PTA or DDC pin group on Ventana. So: - Remove the HDMI function definition of pta pingroup - Define child i2c adapters(ddc & pta) for I2C2 controller Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-ventana.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts69
1 files changed, 63 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index bec8bb297ad8..1dde0d360564 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -64,11 +64,6 @@
64 nvidia,pins = "dap4"; 64 nvidia,pins = "dap4";
65 nvidia,function = "dap4"; 65 nvidia,function = "dap4";
66 }; 66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta { 67 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi"; 69 nvidia,function = "vi";
@@ -98,7 +93,7 @@
98 nvidia,function = "pcie"; 93 nvidia,function = "pcie";
99 }; 94 };
100 hdint { 95 hdint {
101 nvidia,pins = "hdint", "pta"; 96 nvidia,pins = "hdint";
102 nvidia,function = "hdmi"; 97 nvidia,function = "hdmi";
103 }; 98 };
104 i2cp { 99 i2cp {
@@ -129,6 +124,10 @@
129 "lspi", "lvp1", "lvs"; 124 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya"; 125 nvidia,function = "displaya";
131 }; 126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
132 pmc { 131 pmc {
133 nvidia,pins = "pmc"; 132 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on"; 133 nvidia,function = "pwr_on";
@@ -248,6 +247,39 @@
248 nvidia,slew-rate-falling = <3>; 247 nvidia,slew-rate-falling = <3>;
249 }; 248 };
250 }; 249 };
250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
282 };
251 }; 283 };
252 284
253 i2s@70002800 { 285 i2s@70002800 {
@@ -291,6 +323,31 @@
291 clock-frequency = <400000>; 323 clock-frequency = <400000>;
292 }; 324 };
293 325
326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
294 i2c@7000c500 { 351 i2c@7000c500 {
295 status = "okay"; 352 status = "okay";
296 clock-frequency = <400000>; 353 clock-frequency = <400000>;