ARM: SPEAr: DT: Update pinctrl list

This patch updates pinctrl configuration for SPEAr SoC's.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

1 files changed, 17 insertions, 6 deletions

diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 2e4c5727468e..3448d60117ec 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -30,10 +30,14 @@
                         pinctrl-0 = <&state_default>;
 
                         state_default: pinmux {
-                                i2c0-pmx {
+                                i2c0 {
                                         st,pins = "i2c0_grp";
                                         st,function = "i2c0";
                                 };
+                                i2s0 {
+                                        st,pins = "i2s0_grp";
+                                        st,function = "i2s0";
+                                };
                                 i2s1 {
                                         st,pins = "i2s1_grp";
                                         st,function = "i2s1";
@@ -42,6 +46,10 @@
                                         st,pins = "arm_gpio_grp";
                                         st,function = "arm_gpio";
                                 };
+                                clcd {
+                                        st,pins = "clcd_grp" , "clcd_high_res";
+                                        st,function = "clcd";
+                                };
                                 eth {
                                         st,pins = "gmii_grp";
                                         st,function = "gmii";
@@ -74,11 +82,6 @@
                                         st,pins = "i2c_1_2_grp";
                                         st,function = "i2c_1_2";
                                 };
-                                pci {
-                                        st,pins = "pcie0_grp","pcie1_grp",
-                                                "pcie2_grp";
-                                        st,function = "pci";
-                                };
                                 smii {
                                         st,pins = "smii_0_1_2_grp";
                                         st,function = "smii_0_1_2";
@@ -88,6 +91,14 @@
                                                 "nand_16bit_grp";
                                         st,function = "nand";
                                 };
+                                sata {
+                                        st,pins = "sata0_grp";
+                                        st,function = "sata";
+                                };
+                                pcie {
+                                        st,pins = "pcie1_grp", "pcie2_grp";
+                                        st,function = "pci_express";
+                                };
                         };
                 };