ENGR00240987: ARM: dts: enable LDB and LCD support for imx6qdl-sabresd

This is a fast-forward porting of LDB and LCD DTS changes from 3.5.7
kernel.

Along with the changes, the "&ldb" node gets removed from imx6q.dtsi,
since it's only used by community kernel and will conflict with our
internal LDB bindings.

While adding alias for ipu in imx6qdl.dtsi, it also sorts all those
aliases alphabetically.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 23 insertions, 23 deletions

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 39180df78170..59bd248789ea 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -15,11 +15,6 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
@@ -27,6 +22,12 @@
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
                 gpio6 = &gpio7;
+                ipu0 = &ipu1;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         intc: interrupt-controller@00a01000 {
@@ -1231,23 +1232,15 @@
                         };
 
                         ldb: ldb@020e0008 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
-                                gpr = <&gpr>;
+                                reg = <0x020e0000 0x4000>;
+                                clocks = <&clks 135>, <&clks 136>,
+                                         <&clks 39>, <&clks 40>,
+                                         <&clks 41>, <&clks 42>;
+                                clock-names = "ldb_di0", "ldb_di1",
+                                              "ipu1_di0_sel", "ipu1_di1_sel",
+                                              "ipu2_di0_sel", "ipu2_di1_sel";
                                 status = "disabled";
-
-                                lvds-channel@0 {
-                                        reg = <0>;
-                                        crtcs = <&ipu1 0>;
-                                        status = "disabled";
-                                };
-
-                                lvds-channel@1 {
-                                        reg = <1>;
-                                        crtcs = <&ipu1 1>;
-                                        status = "disabled";
-                                };
                         };
 
                         dcic1: dcic@020e4000 {
@@ -1469,8 +1462,11 @@
                         };
 
                         vdoa@021e4000 {
+                                compatible = "fsl,imx6q-vdoa";
                                 reg = <0x021e4000 0x4000>;
                                 interrupts = <0 18 0x04>;
+                                clocks = <&clks 202>;
+                                iram = <&ocram>;
                         };
 
                         uart2: serial@021e8000 {
@@ -1519,13 +1515,17 @@
                 };
 
                 ipu1: ipu@02400000 {
-                        #crtc-cells = <1>;
                         compatible = "fsl,imx6q-ipu";
                         reg = <0x02400000 0x400000>;
                         interrupts = <0 6 0x4 0 5 0x4>;
-                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
-                        clock-names = "bus", "di0", "di1";
+                        clocks = <&clks 130>, <&clks 131>, <&clks 132>,
+                                 <&clks 39>, <&clks 40>,
+                                 <&clks 135>, <&clks 136>;
+                        clock-names = "bus", "di0", "di1",
+                                      "di0_sel", "di1_sel",
+                                      "ldb_di0", "ldb_di1";
                         resets = <&src 2>;
+                        bypass_reset = <0>;
                 };
         };
 };