diff options
| author | Shawn Guo <shawn.guo@freescale.com> | 2013-08-26 23:47:29 -0400 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:01:28 -0400 |
| commit | 04ce7d02f20cf49c84755f06558f5696654f880e (patch) | |
| tree | 9baedf9748cf8f7dc9c08f304bd66beba2fc7956 /arch/arm/boot/dts/imx6qdl.dtsi | |
| parent | 49c0cec9fa0d633b90e73d317702508c5e79ff10 (diff) | |
ENGR00269945: ARM: imx6: maintain pinctrl setting outside bus topology
The patch moves all pinctrl setting nodes outside bus topology using
label, so that we can reduce some indent levels for these nodes and
avoid churning main device nodes structure chunk.
While at it, the patch also sorts those pinctrl setting nodes
alphabetically.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 1335 |
1 files changed, 669 insertions, 666 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index a39b55fd556a..53c6b5240b1a 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -603,672 +603,6 @@ | |||
| 603 | 603 | ||
| 604 | iomuxc: iomuxc@020e0000 { | 604 | iomuxc: iomuxc@020e0000 { |
| 605 | reg = <0x020e0000 0x4000>; | 605 | reg = <0x020e0000 0x4000>; |
| 606 | |||
| 607 | audmux { | ||
| 608 | pinctrl_audmux_1: audmux-1 { | ||
| 609 | fsl,pins = < | ||
| 610 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | ||
| 611 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | ||
| 612 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | ||
| 613 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | ||
| 614 | >; | ||
| 615 | }; | ||
| 616 | |||
| 617 | pinctrl_audmux_2: audmux-2 { | ||
| 618 | fsl,pins = < | ||
| 619 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 620 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 621 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 622 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 623 | >; | ||
| 624 | }; | ||
| 625 | |||
| 626 | pinctrl_audmux_3: audmux-3 { | ||
| 627 | fsl,pins = < | ||
| 628 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 | ||
| 629 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 | ||
| 630 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 | ||
| 631 | >; | ||
| 632 | }; | ||
| 633 | }; | ||
| 634 | |||
| 635 | ecspi1 { | ||
| 636 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 637 | fsl,pins = < | ||
| 638 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 639 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 640 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 641 | >; | ||
| 642 | }; | ||
| 643 | |||
| 644 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 645 | fsl,pins = < | ||
| 646 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | ||
| 647 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | ||
| 648 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | ||
| 649 | >; | ||
| 650 | }; | ||
| 651 | }; | ||
| 652 | |||
| 653 | ecspi3 { | ||
| 654 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 655 | fsl,pins = < | ||
| 656 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 657 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 658 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 659 | >; | ||
| 660 | }; | ||
| 661 | }; | ||
| 662 | |||
| 663 | enet { | ||
| 664 | pinctrl_enet_1: enetgrp-1 { | ||
| 665 | fsl,pins = < | ||
| 666 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 667 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 668 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 669 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 670 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 671 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 672 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 673 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 674 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 675 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 676 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 677 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 678 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 679 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 680 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 681 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 682 | >; | ||
| 683 | }; | ||
| 684 | |||
| 685 | pinctrl_enet_2: enetgrp-2 { | ||
| 686 | fsl,pins = < | ||
| 687 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 688 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 689 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 690 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 691 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 692 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 693 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 694 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 695 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 696 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 697 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 698 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 699 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 700 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 701 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 702 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 703 | >; | ||
| 704 | }; | ||
| 705 | |||
| 706 | pinctrl_enet_3: enetgrp-3 { | ||
| 707 | fsl,pins = < | ||
| 708 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 709 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 710 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 711 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 712 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 713 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 714 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 715 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 716 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 717 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 718 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 719 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 720 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 721 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 722 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 723 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 724 | >; | ||
| 725 | }; | ||
| 726 | }; | ||
| 727 | |||
| 728 | esai { | ||
| 729 | pinctrl_esai_1: esaigrp-1 { | ||
| 730 | fsl,pins = < | ||
| 731 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 | ||
| 732 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 733 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 734 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 735 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 | ||
| 736 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 737 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 738 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 | ||
| 739 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 740 | >; | ||
| 741 | }; | ||
| 742 | |||
| 743 | pinctrl_esai_2: esaigrp-2 { | ||
| 744 | fsl,pins = < | ||
| 745 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 746 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 747 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 748 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 | ||
| 749 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 750 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 751 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 | ||
| 752 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 753 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 | ||
| 754 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 | ||
| 755 | >; | ||
| 756 | }; | ||
| 757 | }; | ||
| 758 | |||
| 759 | flexcan1 { | ||
| 760 | pinctrl_flexcan1_1: flexcan1grp-1 { | ||
| 761 | fsl,pins = < | ||
| 762 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 763 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 764 | >; | ||
| 765 | }; | ||
| 766 | |||
| 767 | pinctrl_flexcan1_2: flexcan1grp-2 { | ||
| 768 | fsl,pins = < | ||
| 769 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 | ||
| 770 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 771 | >; | ||
| 772 | }; | ||
| 773 | }; | ||
| 774 | |||
| 775 | flexcan2 { | ||
| 776 | pinctrl_flexcan2_1: flexcan2grp-1 { | ||
| 777 | fsl,pins = < | ||
| 778 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 | ||
| 779 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 | ||
| 780 | >; | ||
| 781 | }; | ||
| 782 | }; | ||
| 783 | |||
| 784 | gpmi-nand { | ||
| 785 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 786 | fsl,pins = < | ||
| 787 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 788 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 789 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 790 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 791 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 792 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 793 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 794 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 795 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 796 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 797 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 798 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 799 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 800 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 801 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 802 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 803 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 804 | >; | ||
| 805 | }; | ||
| 806 | }; | ||
| 807 | |||
| 808 | hdmi_hdcp { | ||
| 809 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { | ||
| 810 | fsl,pins = < | ||
| 811 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 812 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 813 | >; | ||
| 814 | }; | ||
| 815 | |||
| 816 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { | ||
| 817 | fsl,pins = < | ||
| 818 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 819 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 820 | >; | ||
| 821 | }; | ||
| 822 | |||
| 823 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { | ||
| 824 | fsl,pins = < | ||
| 825 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 826 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 827 | >; | ||
| 828 | }; | ||
| 829 | }; | ||
| 830 | |||
| 831 | hdmi_cec { | ||
| 832 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { | ||
| 833 | fsl,pins = < | ||
| 834 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 835 | >; | ||
| 836 | }; | ||
| 837 | |||
| 838 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { | ||
| 839 | fsl,pins = < | ||
| 840 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 841 | >; | ||
| 842 | }; | ||
| 843 | }; | ||
| 844 | |||
| 845 | i2c1 { | ||
| 846 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 847 | fsl,pins = < | ||
| 848 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 849 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 850 | >; | ||
| 851 | }; | ||
| 852 | |||
| 853 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 854 | fsl,pins = < | ||
| 855 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 856 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 857 | >; | ||
| 858 | }; | ||
| 859 | }; | ||
| 860 | |||
| 861 | i2c2 { | ||
| 862 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 863 | fsl,pins = < | ||
| 864 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 865 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 866 | >; | ||
| 867 | }; | ||
| 868 | |||
| 869 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 870 | fsl,pins = < | ||
| 871 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 872 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 873 | >; | ||
| 874 | }; | ||
| 875 | |||
| 876 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 877 | fsl,pins = < | ||
| 878 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 879 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 880 | >; | ||
| 881 | }; | ||
| 882 | }; | ||
| 883 | |||
| 884 | i2c3 { | ||
| 885 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 886 | fsl,pins = < | ||
| 887 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 888 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 889 | >; | ||
| 890 | }; | ||
| 891 | |||
| 892 | pinctrl_i2c3_2: i2c3grp-2 { | ||
| 893 | fsl,pins = < | ||
| 894 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 895 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 896 | >; | ||
| 897 | }; | ||
| 898 | |||
| 899 | pinctrl_i2c3_3: i2c3grp-3 { | ||
| 900 | fsl,pins = < | ||
| 901 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 902 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | ||
| 903 | >; | ||
| 904 | }; | ||
| 905 | |||
| 906 | pinctrl_i2c3_4: i2c3grp-4 { | ||
| 907 | fsl,pins = < | ||
| 908 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 909 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 910 | >; | ||
| 911 | }; | ||
| 912 | }; | ||
| 913 | |||
| 914 | ipu1 { | ||
| 915 | pinctrl_ipu1_1: ipu1grp-1 { | ||
| 916 | fsl,pins = < | ||
| 917 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | ||
| 918 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 | ||
| 919 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | ||
| 920 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | ||
| 921 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 | ||
| 922 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | ||
| 923 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | ||
| 924 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | ||
| 925 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | ||
| 926 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | ||
| 927 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | ||
| 928 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | ||
| 929 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | ||
| 930 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | ||
| 931 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | ||
| 932 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | ||
| 933 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | ||
| 934 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | ||
| 935 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | ||
| 936 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | ||
| 937 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | ||
| 938 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | ||
| 939 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | ||
| 940 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | ||
| 941 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | ||
| 942 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | ||
| 943 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | ||
| 944 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | ||
| 945 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | ||
| 946 | >; | ||
| 947 | }; | ||
| 948 | |||
| 949 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ | ||
| 950 | fsl,pins = < | ||
| 951 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 952 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 953 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 954 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 955 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 956 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 957 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 958 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 959 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 | ||
| 960 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 961 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 962 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 963 | >; | ||
| 964 | }; | ||
| 965 | |||
| 966 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ | ||
| 967 | fsl,pins = < | ||
| 968 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 | ||
| 969 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 | ||
| 970 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 | ||
| 971 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 | ||
| 972 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 | ||
| 973 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 | ||
| 974 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 | ||
| 975 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 | ||
| 976 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 977 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 978 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 979 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 980 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 981 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 982 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 983 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 984 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 985 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 986 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 987 | >; | ||
| 988 | }; | ||
| 989 | }; | ||
| 990 | |||
| 991 | mlb { | ||
| 992 | pinctrl_mlb_1: mlbgrp-1 { | ||
| 993 | fsl,pins = < | ||
| 994 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 | ||
| 995 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 996 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 997 | >; | ||
| 998 | }; | ||
| 999 | |||
| 1000 | pinctrl_mlb_2: mlbgrp-2 { | ||
| 1001 | fsl,pins = < | ||
| 1002 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 | ||
| 1003 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 1004 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 1005 | >; | ||
| 1006 | }; | ||
| 1007 | }; | ||
| 1008 | |||
| 1009 | pwm1 { | ||
| 1010 | pinctrl_pwm1_1: pwm1grp-1 { | ||
| 1011 | fsl,pins = < | ||
| 1012 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 1013 | >; | ||
| 1014 | }; | ||
| 1015 | }; | ||
| 1016 | |||
| 1017 | pwm3 { | ||
| 1018 | pinctrl_pwm3_1: pwm3grp-1 { | ||
| 1019 | fsl,pins = < | ||
| 1020 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | ||
| 1021 | >; | ||
| 1022 | }; | ||
| 1023 | }; | ||
| 1024 | |||
| 1025 | spdif { | ||
| 1026 | pinctrl_spdif_1: spdifgrp-1 { | ||
| 1027 | fsl,pins = < | ||
| 1028 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | ||
| 1029 | >; | ||
| 1030 | }; | ||
| 1031 | |||
| 1032 | pinctrl_spdif_2: spdifgrp-2 { | ||
| 1033 | fsl,pins = < | ||
| 1034 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 | ||
| 1035 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 | ||
| 1036 | >; | ||
| 1037 | }; | ||
| 1038 | }; | ||
| 1039 | |||
| 1040 | uart1 { | ||
| 1041 | pinctrl_uart1_1: uart1grp-1 { | ||
| 1042 | fsl,pins = < | ||
| 1043 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 1044 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 1045 | >; | ||
| 1046 | }; | ||
| 1047 | }; | ||
| 1048 | |||
| 1049 | uart2 { | ||
| 1050 | pinctrl_uart2_1: uart2grp-1 { | ||
| 1051 | fsl,pins = < | ||
| 1052 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 1053 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 1054 | >; | ||
| 1055 | }; | ||
| 1056 | |||
| 1057 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ | ||
| 1058 | fsl,pins = < | ||
| 1059 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | ||
| 1060 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | ||
| 1061 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | ||
| 1062 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | ||
| 1063 | >; | ||
| 1064 | }; | ||
| 1065 | }; | ||
| 1066 | |||
| 1067 | uart3 { | ||
| 1068 | pinctrl_uart3_1: uart3grp-1 { | ||
| 1069 | fsl,pins = < | ||
| 1070 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | ||
| 1071 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | ||
| 1072 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | ||
| 1073 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1074 | >; | ||
| 1075 | }; | ||
| 1076 | }; | ||
| 1077 | |||
| 1078 | uart4 { | ||
| 1079 | pinctrl_uart4_1: uart4grp-1 { | ||
| 1080 | fsl,pins = < | ||
| 1081 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 1082 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 1083 | >; | ||
| 1084 | }; | ||
| 1085 | }; | ||
| 1086 | |||
| 1087 | usbotg { | ||
| 1088 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 1089 | fsl,pins = < | ||
| 1090 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 1091 | >; | ||
| 1092 | }; | ||
| 1093 | |||
| 1094 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 1095 | fsl,pins = < | ||
| 1096 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 1097 | >; | ||
| 1098 | }; | ||
| 1099 | }; | ||
| 1100 | |||
| 1101 | usbh2 { | ||
| 1102 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 1103 | fsl,pins = < | ||
| 1104 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 | ||
| 1105 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 | ||
| 1106 | >; | ||
| 1107 | }; | ||
| 1108 | |||
| 1109 | pinctrl_usbh2_2: usbh2grp-2 { | ||
| 1110 | fsl,pins = < | ||
| 1111 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 | ||
| 1112 | >; | ||
| 1113 | }; | ||
| 1114 | }; | ||
| 1115 | |||
| 1116 | usbh3 { | ||
| 1117 | pinctrl_usbh3_1: usbh3grp-1 { | ||
| 1118 | fsl,pins = < | ||
| 1119 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 | ||
| 1120 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 | ||
| 1121 | >; | ||
| 1122 | }; | ||
| 1123 | |||
| 1124 | pinctrl_usbh3_2: usbh3grp-2 { | ||
| 1125 | fsl,pins = < | ||
| 1126 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 | ||
| 1127 | >; | ||
| 1128 | }; | ||
| 1129 | }; | ||
| 1130 | |||
| 1131 | usdhc2 { | ||
| 1132 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 1133 | fsl,pins = < | ||
| 1134 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1135 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1136 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1137 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1138 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1139 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1140 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 1141 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 1142 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 1143 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 1144 | >; | ||
| 1145 | }; | ||
| 1146 | |||
| 1147 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 1148 | fsl,pins = < | ||
| 1149 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1150 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1151 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1152 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1153 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1154 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1155 | >; | ||
| 1156 | }; | ||
| 1157 | }; | ||
| 1158 | |||
| 1159 | usdhc3 { | ||
| 1160 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 1161 | fsl,pins = < | ||
| 1162 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1163 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1164 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1165 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1166 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1167 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1168 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 1169 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 1170 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 1171 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 1172 | >; | ||
| 1173 | }; | ||
| 1174 | |||
| 1175 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 1176 | fsl,pins = < | ||
| 1177 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1178 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1179 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1180 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1181 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1182 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1183 | >; | ||
| 1184 | }; | ||
| 1185 | }; | ||
| 1186 | |||
| 1187 | usdhc4 { | ||
| 1188 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| 1189 | fsl,pins = < | ||
| 1190 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1191 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1192 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1193 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1194 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1195 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1196 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 1197 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 1198 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 1199 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 1200 | >; | ||
| 1201 | }; | ||
| 1202 | |||
| 1203 | pinctrl_usdhc4_2: usdhc4grp-2 { | ||
| 1204 | fsl,pins = < | ||
| 1205 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1206 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1207 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1208 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1209 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1210 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1211 | >; | ||
| 1212 | }; | ||
| 1213 | }; | ||
| 1214 | |||
| 1215 | weim { | ||
| 1216 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 1217 | fsl,pins = < | ||
| 1218 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 1219 | >; | ||
| 1220 | }; | ||
| 1221 | |||
| 1222 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 1223 | fsl,pins = < | ||
| 1224 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 1225 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 1226 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 1227 | /* data */ | ||
| 1228 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 1229 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 1230 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 1231 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 1232 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 1233 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 1234 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 1235 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 1236 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 1237 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 1238 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 1239 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 1240 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 1241 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 1242 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 1243 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 1244 | /* address */ | ||
| 1245 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 1246 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 1247 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 1248 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 1249 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 1250 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 1251 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 1252 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 1253 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 1254 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 1255 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 1256 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 1257 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 1258 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 1259 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 1260 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 1261 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 1262 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 1263 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 1264 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 1265 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 1266 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 1267 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 1268 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 1269 | >; | ||
| 1270 | }; | ||
| 1271 | }; | ||
| 1272 | }; | 606 | }; |
| 1273 | 607 | ||
| 1274 | ldb: ldb@020e0008 { | 608 | ldb: ldb@020e0008 { |
| @@ -1578,3 +912,672 @@ | |||
| 1578 | }; | 912 | }; |
| 1579 | }; | 913 | }; |
| 1580 | }; | 914 | }; |
| 915 | |||
| 916 | |||
| 917 | &iomuxc { | ||
| 918 | audmux { | ||
| 919 | pinctrl_audmux_1: audmux-1 { | ||
| 920 | fsl,pins = < | ||
| 921 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | ||
| 922 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | ||
| 923 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | ||
| 924 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | ||
| 925 | >; | ||
| 926 | }; | ||
| 927 | |||
| 928 | pinctrl_audmux_2: audmux-2 { | ||
| 929 | fsl,pins = < | ||
| 930 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 931 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 932 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 933 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 934 | >; | ||
| 935 | }; | ||
| 936 | |||
| 937 | pinctrl_audmux_3: audmux-3 { | ||
| 938 | fsl,pins = < | ||
| 939 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 | ||
| 940 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 | ||
| 941 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 | ||
| 942 | >; | ||
| 943 | }; | ||
| 944 | }; | ||
| 945 | |||
| 946 | ecspi1 { | ||
| 947 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 948 | fsl,pins = < | ||
| 949 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 950 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 951 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 952 | >; | ||
| 953 | }; | ||
| 954 | |||
| 955 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 956 | fsl,pins = < | ||
| 957 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | ||
| 958 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | ||
| 959 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | ||
| 960 | >; | ||
| 961 | }; | ||
| 962 | }; | ||
| 963 | |||
| 964 | ecspi3 { | ||
| 965 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 966 | fsl,pins = < | ||
| 967 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 968 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 969 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 970 | >; | ||
| 971 | }; | ||
| 972 | }; | ||
| 973 | |||
| 974 | enet { | ||
| 975 | pinctrl_enet_1: enetgrp-1 { | ||
| 976 | fsl,pins = < | ||
| 977 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 978 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 979 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 980 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 981 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 982 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 983 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 984 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 985 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 986 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 987 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 988 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 989 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 990 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 991 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 992 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 993 | >; | ||
| 994 | }; | ||
| 995 | |||
| 996 | pinctrl_enet_2: enetgrp-2 { | ||
| 997 | fsl,pins = < | ||
| 998 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 999 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 1000 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 1001 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 1002 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 1003 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 1004 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 1005 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 1006 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 1007 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 1008 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 1009 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 1010 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 1011 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 1012 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 1013 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 1014 | >; | ||
| 1015 | }; | ||
| 1016 | |||
| 1017 | pinctrl_enet_3: enetgrp-3 { | ||
| 1018 | fsl,pins = < | ||
| 1019 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 1020 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 1021 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 1022 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 1023 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 1024 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 1025 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 1026 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 1027 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 1028 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 1029 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 1030 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 1031 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 1032 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 1033 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 1034 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 1035 | >; | ||
| 1036 | }; | ||
| 1037 | }; | ||
| 1038 | |||
| 1039 | esai { | ||
| 1040 | pinctrl_esai_1: esaigrp-1 { | ||
| 1041 | fsl,pins = < | ||
| 1042 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 | ||
| 1043 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 1044 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 1045 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 1046 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 | ||
| 1047 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 1048 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 1049 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 | ||
| 1050 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 1051 | >; | ||
| 1052 | }; | ||
| 1053 | |||
| 1054 | pinctrl_esai_2: esaigrp-2 { | ||
| 1055 | fsl,pins = < | ||
| 1056 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 1057 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 1058 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 1059 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 | ||
| 1060 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 1061 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 1062 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 | ||
| 1063 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 1064 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 | ||
| 1065 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 | ||
| 1066 | >; | ||
| 1067 | }; | ||
| 1068 | }; | ||
| 1069 | |||
| 1070 | flexcan1 { | ||
| 1071 | pinctrl_flexcan1_1: flexcan1grp-1 { | ||
| 1072 | fsl,pins = < | ||
| 1073 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 1074 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 1075 | >; | ||
| 1076 | }; | ||
| 1077 | |||
| 1078 | pinctrl_flexcan1_2: flexcan1grp-2 { | ||
| 1079 | fsl,pins = < | ||
| 1080 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 | ||
| 1081 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 1082 | >; | ||
| 1083 | }; | ||
| 1084 | }; | ||
| 1085 | |||
| 1086 | flexcan2 { | ||
| 1087 | pinctrl_flexcan2_1: flexcan2grp-1 { | ||
| 1088 | fsl,pins = < | ||
| 1089 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 | ||
| 1090 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 | ||
| 1091 | >; | ||
| 1092 | }; | ||
| 1093 | }; | ||
| 1094 | |||
| 1095 | gpmi-nand { | ||
| 1096 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 1097 | fsl,pins = < | ||
| 1098 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 1099 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 1100 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 1101 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 1102 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 1103 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 1104 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 1105 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 1106 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 1107 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 1108 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 1109 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 1110 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 1111 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 1112 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 1113 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 1114 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 1115 | >; | ||
| 1116 | }; | ||
| 1117 | }; | ||
| 1118 | |||
| 1119 | hdmi_hdcp { | ||
| 1120 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { | ||
| 1121 | fsl,pins = < | ||
| 1122 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 1123 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 1124 | >; | ||
| 1125 | }; | ||
| 1126 | |||
| 1127 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { | ||
| 1128 | fsl,pins = < | ||
| 1129 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 1130 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 1131 | >; | ||
| 1132 | }; | ||
| 1133 | |||
| 1134 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { | ||
| 1135 | fsl,pins = < | ||
| 1136 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 1137 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 1138 | >; | ||
| 1139 | }; | ||
| 1140 | }; | ||
| 1141 | |||
| 1142 | hdmi_cec { | ||
| 1143 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { | ||
| 1144 | fsl,pins = < | ||
| 1145 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 1146 | >; | ||
| 1147 | }; | ||
| 1148 | |||
| 1149 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { | ||
| 1150 | fsl,pins = < | ||
| 1151 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 1152 | >; | ||
| 1153 | }; | ||
| 1154 | }; | ||
| 1155 | |||
| 1156 | i2c1 { | ||
| 1157 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 1158 | fsl,pins = < | ||
| 1159 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 1160 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 1161 | >; | ||
| 1162 | }; | ||
| 1163 | |||
| 1164 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 1165 | fsl,pins = < | ||
| 1166 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 1167 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 1168 | >; | ||
| 1169 | }; | ||
| 1170 | }; | ||
| 1171 | |||
| 1172 | i2c2 { | ||
| 1173 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 1174 | fsl,pins = < | ||
| 1175 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 1176 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 1177 | >; | ||
| 1178 | }; | ||
| 1179 | |||
| 1180 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 1181 | fsl,pins = < | ||
| 1182 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 1183 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 1184 | >; | ||
| 1185 | }; | ||
| 1186 | |||
| 1187 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 1188 | fsl,pins = < | ||
| 1189 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 1190 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 1191 | >; | ||
| 1192 | }; | ||
| 1193 | }; | ||
| 1194 | |||
| 1195 | i2c3 { | ||
| 1196 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 1197 | fsl,pins = < | ||
| 1198 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 1199 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 1200 | >; | ||
| 1201 | }; | ||
| 1202 | |||
| 1203 | pinctrl_i2c3_2: i2c3grp-2 { | ||
| 1204 | fsl,pins = < | ||
| 1205 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 1206 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 1207 | >; | ||
| 1208 | }; | ||
| 1209 | |||
| 1210 | pinctrl_i2c3_3: i2c3grp-3 { | ||
| 1211 | fsl,pins = < | ||
| 1212 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 1213 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | ||
| 1214 | >; | ||
| 1215 | }; | ||
| 1216 | |||
| 1217 | pinctrl_i2c3_4: i2c3grp-4 { | ||
| 1218 | fsl,pins = < | ||
| 1219 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 1220 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 1221 | >; | ||
| 1222 | }; | ||
| 1223 | }; | ||
| 1224 | |||
| 1225 | ipu1 { | ||
| 1226 | pinctrl_ipu1_1: ipu1grp-1 { | ||
| 1227 | fsl,pins = < | ||
| 1228 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | ||
| 1229 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 | ||
| 1230 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | ||
| 1231 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | ||
| 1232 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 | ||
| 1233 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | ||
| 1234 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | ||
| 1235 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | ||
| 1236 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | ||
| 1237 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | ||
| 1238 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | ||
| 1239 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | ||
| 1240 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | ||
| 1241 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | ||
| 1242 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | ||
| 1243 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | ||
| 1244 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | ||
| 1245 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | ||
| 1246 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | ||
| 1247 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | ||
| 1248 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | ||
| 1249 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | ||
| 1250 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | ||
| 1251 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | ||
| 1252 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | ||
| 1253 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | ||
| 1254 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | ||
| 1255 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | ||
| 1256 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | ||
| 1257 | >; | ||
| 1258 | }; | ||
| 1259 | |||
| 1260 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ | ||
| 1261 | fsl,pins = < | ||
| 1262 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 1263 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 1264 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 1265 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 1266 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 1267 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 1268 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 1269 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 1270 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 | ||
| 1271 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 1272 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 1273 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 1274 | >; | ||
| 1275 | }; | ||
| 1276 | |||
| 1277 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ | ||
| 1278 | fsl,pins = < | ||
| 1279 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 | ||
| 1280 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 | ||
| 1281 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 | ||
| 1282 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 | ||
| 1283 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 | ||
| 1284 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 | ||
| 1285 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 | ||
| 1286 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 | ||
| 1287 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 1288 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 1289 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 1290 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 1291 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 1292 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 1293 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 1294 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 1295 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 1296 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 1297 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 1298 | >; | ||
| 1299 | }; | ||
| 1300 | }; | ||
| 1301 | |||
| 1302 | mlb { | ||
| 1303 | pinctrl_mlb_1: mlbgrp-1 { | ||
| 1304 | fsl,pins = < | ||
| 1305 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 | ||
| 1306 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 1307 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 1308 | >; | ||
| 1309 | }; | ||
| 1310 | |||
| 1311 | pinctrl_mlb_2: mlbgrp-2 { | ||
| 1312 | fsl,pins = < | ||
| 1313 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 | ||
| 1314 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 1315 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 1316 | >; | ||
| 1317 | }; | ||
| 1318 | }; | ||
| 1319 | |||
| 1320 | pwm1 { | ||
| 1321 | pinctrl_pwm1_1: pwm1grp-1 { | ||
| 1322 | fsl,pins = < | ||
| 1323 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 1324 | >; | ||
| 1325 | }; | ||
| 1326 | }; | ||
| 1327 | |||
| 1328 | pwm3 { | ||
| 1329 | pinctrl_pwm3_1: pwm3grp-1 { | ||
| 1330 | fsl,pins = < | ||
| 1331 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | ||
| 1332 | >; | ||
| 1333 | }; | ||
| 1334 | }; | ||
| 1335 | |||
| 1336 | spdif { | ||
| 1337 | pinctrl_spdif_1: spdifgrp-1 { | ||
| 1338 | fsl,pins = < | ||
| 1339 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | ||
| 1340 | >; | ||
| 1341 | }; | ||
| 1342 | |||
| 1343 | pinctrl_spdif_2: spdifgrp-2 { | ||
| 1344 | fsl,pins = < | ||
| 1345 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 | ||
| 1346 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 | ||
| 1347 | >; | ||
| 1348 | }; | ||
| 1349 | }; | ||
| 1350 | |||
| 1351 | uart1 { | ||
| 1352 | pinctrl_uart1_1: uart1grp-1 { | ||
| 1353 | fsl,pins = < | ||
| 1354 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 1355 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 1356 | >; | ||
| 1357 | }; | ||
| 1358 | }; | ||
| 1359 | |||
| 1360 | uart2 { | ||
| 1361 | pinctrl_uart2_1: uart2grp-1 { | ||
| 1362 | fsl,pins = < | ||
| 1363 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 1364 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 1365 | >; | ||
| 1366 | }; | ||
| 1367 | |||
| 1368 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ | ||
| 1369 | fsl,pins = < | ||
| 1370 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | ||
| 1371 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | ||
| 1372 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | ||
| 1373 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | ||
| 1374 | >; | ||
| 1375 | }; | ||
| 1376 | }; | ||
| 1377 | |||
| 1378 | uart3 { | ||
| 1379 | pinctrl_uart3_1: uart3grp-1 { | ||
| 1380 | fsl,pins = < | ||
| 1381 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | ||
| 1382 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | ||
| 1383 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | ||
| 1384 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1385 | >; | ||
| 1386 | }; | ||
| 1387 | }; | ||
| 1388 | |||
| 1389 | uart4 { | ||
| 1390 | pinctrl_uart4_1: uart4grp-1 { | ||
| 1391 | fsl,pins = < | ||
| 1392 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 1393 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 1394 | >; | ||
| 1395 | }; | ||
| 1396 | }; | ||
| 1397 | |||
| 1398 | usbotg { | ||
| 1399 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 1400 | fsl,pins = < | ||
| 1401 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 1402 | >; | ||
| 1403 | }; | ||
| 1404 | |||
| 1405 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 1406 | fsl,pins = < | ||
| 1407 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 1408 | >; | ||
| 1409 | }; | ||
| 1410 | }; | ||
| 1411 | |||
| 1412 | usbh2 { | ||
| 1413 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 1414 | fsl,pins = < | ||
| 1415 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 | ||
| 1416 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 | ||
| 1417 | >; | ||
| 1418 | }; | ||
| 1419 | |||
| 1420 | pinctrl_usbh2_2: usbh2grp-2 { | ||
| 1421 | fsl,pins = < | ||
| 1422 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 | ||
| 1423 | >; | ||
| 1424 | }; | ||
| 1425 | }; | ||
| 1426 | |||
| 1427 | usbh3 { | ||
| 1428 | pinctrl_usbh3_1: usbh3grp-1 { | ||
| 1429 | fsl,pins = < | ||
| 1430 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 | ||
| 1431 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 | ||
| 1432 | >; | ||
| 1433 | }; | ||
| 1434 | |||
| 1435 | pinctrl_usbh3_2: usbh3grp-2 { | ||
| 1436 | fsl,pins = < | ||
| 1437 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 | ||
| 1438 | >; | ||
| 1439 | }; | ||
| 1440 | }; | ||
| 1441 | |||
| 1442 | usdhc2 { | ||
| 1443 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 1444 | fsl,pins = < | ||
| 1445 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1446 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1447 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1448 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1449 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1450 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1451 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 1452 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 1453 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 1454 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 1455 | >; | ||
| 1456 | }; | ||
| 1457 | |||
| 1458 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 1459 | fsl,pins = < | ||
| 1460 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1461 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1462 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1463 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1464 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1465 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1466 | >; | ||
| 1467 | }; | ||
| 1468 | }; | ||
| 1469 | |||
| 1470 | usdhc3 { | ||
| 1471 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 1472 | fsl,pins = < | ||
| 1473 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1474 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1475 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1476 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1477 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1478 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1479 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 1480 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 1481 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 1482 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 1483 | >; | ||
| 1484 | }; | ||
| 1485 | |||
| 1486 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 1487 | fsl,pins = < | ||
| 1488 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1489 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1490 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1491 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1492 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1493 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1494 | >; | ||
| 1495 | }; | ||
| 1496 | }; | ||
| 1497 | |||
| 1498 | usdhc4 { | ||
| 1499 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| 1500 | fsl,pins = < | ||
| 1501 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1502 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1503 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1504 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1505 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1506 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1507 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 1508 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 1509 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 1510 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 1511 | >; | ||
| 1512 | }; | ||
| 1513 | |||
| 1514 | pinctrl_usdhc4_2: usdhc4grp-2 { | ||
| 1515 | fsl,pins = < | ||
| 1516 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1517 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1518 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1519 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1520 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1521 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1522 | >; | ||
| 1523 | }; | ||
| 1524 | }; | ||
| 1525 | |||
| 1526 | weim { | ||
| 1527 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 1528 | fsl,pins = < | ||
| 1529 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 1530 | >; | ||
| 1531 | }; | ||
| 1532 | |||
| 1533 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 1534 | fsl,pins = < | ||
| 1535 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 1536 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 1537 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 1538 | /* data */ | ||
| 1539 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 1540 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 1541 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 1542 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 1543 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 1544 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 1545 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 1546 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 1547 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 1548 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 1549 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 1550 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 1551 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 1552 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 1553 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 1554 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 1555 | /* address */ | ||
| 1556 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 1557 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 1558 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 1559 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 1560 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 1561 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 1562 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 1563 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 1564 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 1565 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 1566 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 1567 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 1568 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 1569 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 1570 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 1571 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 1572 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 1573 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 1574 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 1575 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 1576 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 1577 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 1578 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 1579 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 1580 | >; | ||
| 1581 | }; | ||
| 1582 | }; | ||
| 1583 | }; | ||