diff options
author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2012-11-18 18:30:01 -0500 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2012-11-18 18:50:56 -0500 |
commit | c58c0c5acceb8acd3d447483a744e8a4a7c27f26 (patch) | |
tree | 0eaf3cf08eab1ca4d26bd6755b2ad74e601561c6 /arch/arm/boot/dts/at91sam9x5.dtsi | |
parent | 9e3129e937e2f178d2a003ea45765e5e63e34665 (diff) |
ARM: at91: dt: at91sam9260: split rts and cts pinctrl not
as we just use the rts and not the rts & cts for rs485
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9x5.dtsi')
-rw-r--r-- | arch/arm/boot/dts/at91sam9x5.dtsi | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 9dac00693faf..3642ab1eeaf6 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
@@ -133,10 +133,14 @@ | |||
133 | 0 1 0x1 0x0>; /* PA1 periph A */ | 133 | 0 1 0x1 0x0>; /* PA1 periph A */ |
134 | }; | 134 | }; |
135 | 135 | ||
136 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | 136 | pinctrl_usart0_rts: usart0_rts-0 { |
137 | atmel,pins = | 137 | atmel,pins = |
138 | <0 2 0x1 0x0 /* PA2 periph A */ | 138 | <0 2 0x1 0x0>; /* PA2 periph A */ |
139 | 0 3 0x1 0x0>; /* PA3 periph A */ | 139 | }; |
140 | |||
141 | pinctrl_usart0_cts: usart0_cts-0 { | ||
142 | atmel,pins = | ||
143 | <0 3 0x1 0x0>; /* PA3 periph A */ | ||
140 | }; | 144 | }; |
141 | }; | 145 | }; |
142 | 146 | ||
@@ -147,10 +151,14 @@ | |||
147 | 0 6 0x1 0x0>; /* PA6 periph A */ | 151 | 0 6 0x1 0x0>; /* PA6 periph A */ |
148 | }; | 152 | }; |
149 | 153 | ||
150 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | 154 | pinctrl_usart1_rts: usart1_rts-0 { |
155 | atmel,pins = | ||
156 | <3 27 0x3 0x0>; /* PC27 periph C */ | ||
157 | }; | ||
158 | |||
159 | pinctrl_usart1_cts: usart1_cts-0 { | ||
151 | atmel,pins = | 160 | atmel,pins = |
152 | <3 27 0x3 0x0 /* PC27 periph C */ | 161 | <3 28 0x3 0x0>; /* PC28 periph C */ |
153 | 3 28 0x3 0x0>; /* PC28 periph C */ | ||
154 | }; | 162 | }; |
155 | }; | 163 | }; |
156 | 164 | ||
@@ -161,10 +169,14 @@ | |||
161 | 0 8 0x1 0x0>; /* PA8 periph A */ | 169 | 0 8 0x1 0x0>; /* PA8 periph A */ |
162 | }; | 170 | }; |
163 | 171 | ||
164 | pinctrl_uart2_rts_cts: uart2_rts_cts-0 { | 172 | pinctrl_uart2_rts: uart2_rts-0 { |
165 | atmel,pins = | 173 | atmel,pins = |
166 | <0 0 0x2 0x0 /* PB0 periph B */ | 174 | <0 0 0x2 0x0>; /* PB0 periph B */ |
167 | 0 1 0x2 0x0>; /* PB1 periph B */ | 175 | }; |
176 | |||
177 | pinctrl_uart2_cts: uart2_cts-0 { | ||
178 | atmel,pins = | ||
179 | <0 1 0x2 0x0>; /* PB1 periph B */ | ||
168 | }; | 180 | }; |
169 | }; | 181 | }; |
170 | 182 | ||
@@ -175,10 +187,14 @@ | |||
175 | 3 23 0x2 0x0>; /* PC23 periph B */ | 187 | 3 23 0x2 0x0>; /* PC23 periph B */ |
176 | }; | 188 | }; |
177 | 189 | ||
178 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | 190 | pinctrl_usart3_rts: usart3_rts-0 { |
191 | atmel,pins = | ||
192 | <3 24 0x2 0x0>; /* PC24 periph B */ | ||
193 | }; | ||
194 | |||
195 | pinctrl_usart3_cts: usart3_cts-0 { | ||
179 | atmel,pins = | 196 | atmel,pins = |
180 | <3 24 0x2 0x0 /* PC24 periph B */ | 197 | <3 25 0x2 0x0>; /* PC25 periph B */ |
181 | 3 25 0x2 0x0>; /* PC25 periph B */ | ||
182 | }; | 198 | }; |
183 | }; | 199 | }; |
184 | 200 | ||