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authorH. Peter Anvin <hpa@zytor.com>2008-08-27 22:17:07 -0400
committerH. Peter Anvin <hpa@zytor.com>2008-08-27 22:17:07 -0400
commitb30a72a7edfc64c8929104d5c2178aca489aa559 (patch)
tree2b26c155c318d08d946bd2d70cf815dcdb29a243 /arch/alpha/include/asm/auxvec.h
parentf1c5d30e1d79bbfb60eaf189db862d3cb2bcac92 (diff)
parentc1b362e3b4d331a63915b268a33207311a439d60 (diff)
Merge branch 'x86/urgent' into x86/cpu
Conflicts: arch/x86/kernel/cpu/cyrix.c
Diffstat (limited to 'arch/alpha/include/asm/auxvec.h')
-rw-r--r--arch/alpha/include/asm/auxvec.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/auxvec.h b/arch/alpha/include/asm/auxvec.h
new file mode 100644
index 000000000000..e96fe880e310
--- /dev/null
+++ b/arch/alpha/include/asm/auxvec.h
@@ -0,0 +1,24 @@
1#ifndef __ASM_ALPHA_AUXVEC_H
2#define __ASM_ALPHA_AUXVEC_H
3
4/* Reserve these numbers for any future use of a VDSO. */
5#if 0
6#define AT_SYSINFO 32
7#define AT_SYSINFO_EHDR 33
8#endif
9
10/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
11 value is -1, then the cache doesn't exist. Otherwise:
12
13 bit 0-3: Cache set-associativity; 0 means fully associative.
14 bit 4-7: Log2 of cacheline size.
15 bit 8-31: Size of the entire cache >> 8.
16 bit 32-63: Reserved.
17*/
18
19#define AT_L1I_CACHESHAPE 34
20#define AT_L1D_CACHESHAPE 35
21#define AT_L2_CACHESHAPE 36
22#define AT_L3_CACHESHAPE 37
23
24#endif /* __ASM_ALPHA_AUXVEC_H */