diff options
| author | Jingoo Han <jg1.han@samsung.com> | 2013-07-31 04:14:10 -0400 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:01:30 -0400 |
| commit | 0a42956e57a08e7b9e8629c87c5d6e83cb4f2702 (patch) | |
| tree | 46c58854b2805af61fc4e6f4f30ebf94bf8ffcb3 /Documentation | |
| parent | da6f04e46fe7c37f55e1136c139537fda0f0d575 (diff) | |
PCI: exynos: Split into Synopsys part and Exynos part
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.
Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/designware-pcie.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index e2371f5cdebe..eabcb4b5db6e 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt | |||
| @@ -18,6 +18,7 @@ Required properties: | |||
| 18 | - interrupt-map-mask and interrupt-map: standard PCI properties | 18 | - interrupt-map-mask and interrupt-map: standard PCI properties |
| 19 | to define the mapping of the PCIe interface to interrupt | 19 | to define the mapping of the PCIe interface to interrupt |
| 20 | numbers. | 20 | numbers. |
| 21 | - num-lanes: number of lanes to use | ||
| 21 | - reset-gpio: gpio pin number of power good signal | 22 | - reset-gpio: gpio pin number of power good signal |
| 22 | 23 | ||
| 23 | Example: | 24 | Example: |
| @@ -41,6 +42,7 @@ SoC specific DT Entry: | |||
| 41 | #interrupt-cells = <1>; | 42 | #interrupt-cells = <1>; |
| 42 | interrupt-map-mask = <0 0 0 0>; | 43 | interrupt-map-mask = <0 0 0 0>; |
| 43 | interrupt-map = <0x0 0 &gic 53>; | 44 | interrupt-map = <0x0 0 &gic 53>; |
| 45 | num-lanes = <4>; | ||
| 44 | }; | 46 | }; |
| 45 | 47 | ||
| 46 | pcie@2a0000 { | 48 | pcie@2a0000 { |
| @@ -60,6 +62,7 @@ SoC specific DT Entry: | |||
| 60 | #interrupt-cells = <1>; | 62 | #interrupt-cells = <1>; |
| 61 | interrupt-map-mask = <0 0 0 0>; | 63 | interrupt-map-mask = <0 0 0 0>; |
| 62 | interrupt-map = <0x0 0 &gic 56>; | 64 | interrupt-map = <0x0 0 &gic 56>; |
| 65 | num-lanes = <4>; | ||
| 63 | }; | 66 | }; |
| 64 | 67 | ||
| 65 | Board specific DT Entry: | 68 | Board specific DT Entry: |