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author | Jaroslav Kysela <perex@suse.cz> | 2006-03-22 05:02:08 -0500 |
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committer | Jaroslav Kysela <perex@suse.cz> | 2006-03-22 05:02:08 -0500 |
commit | 5501972e0b5857bc8354770d900ceb9b40c7f6b7 (patch) | |
tree | ff239422827c4cd54d2998f8851304255de31b38 /Documentation/video4linux/cpia2_overview.txt | |
parent | 9d2f928ddf64ca0361562e30faf584cd33055c60 (diff) | |
parent | e952f31bce6e9f64db01f607abc46529ba57ac9e (diff) |
Merge with rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
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-rw-r--r-- | Documentation/video4linux/cpia2_overview.txt | 38 |
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1 | Programmer's View of Cpia2 | ||
2 | |||
3 | Cpia2 is the second generation video coprocessor from VLSI Vision Ltd (now a | ||
4 | division of ST Microelectronics). There are two versions. The first is the | ||
5 | STV0672, which is capable of up to 30 frames per second (fps) in frame sizes | ||
6 | up to CIF, and 15 fps for VGA frames. The STV0676 is an improved version, | ||
7 | which can handle up to 30 fps VGA. Both coprocessors can be attached to two | ||
8 | CMOS sensors - the vvl6410 CIF sensor and the vvl6500 VGA sensor. These will | ||
9 | be referred to as the 410 and the 500 sensors, or the CIF and VGA sensors. | ||
10 | |||
11 | The two chipsets operate almost identically. The core is an 8051 processor, | ||
12 | running two different versions of firmware. The 672 runs the VP4 video | ||
13 | processor code, the 676 runs VP5. There are a few differences in register | ||
14 | mappings for the two chips. In these cases, the symbols defined in the | ||
15 | header files are marked with VP4 or VP5 as part of the symbol name. | ||
16 | |||
17 | The cameras appear externally as three sets of registers. Setting register | ||
18 | values is the only way to control the camera. Some settings are | ||
19 | interdependant, such as the sequence required to power up the camera. I will | ||
20 | try to make note of all of these cases. | ||
21 | |||
22 | The register sets are called blocks. Block 0 is the system block. This | ||
23 | section is always powered on when the camera is plugged in. It contains | ||
24 | registers that control housekeeping functions such as powering up the video | ||
25 | processor. The video processor is the VP block. These registers control | ||
26 | how the video from the sensor is processed. Examples are timing registers, | ||
27 | user mode (vga, qvga), scaling, cropping, framerates, and so on. The last | ||
28 | block is the video compressor (VC). The video stream sent from the camera is | ||
29 | compressed as Motion JPEG (JPEGA). The VC controls all of the compression | ||
30 | parameters. Looking at the file cpia2_registers.h, you can get a full view | ||
31 | of these registers and the possible values for most of them. | ||
32 | |||
33 | One or more registers can be set or read by sending a usb control message to | ||
34 | the camera. There are three modes for this. Block mode requests a number | ||
35 | of contiguous registers. Random mode reads or writes random registers with | ||
36 | a tuple structure containing address/value pairs. The repeat mode is only | ||
37 | used by VP4 to load a firmware patch. It contains a starting address and | ||
38 | a sequence of bytes to be written into a gpio port. \ No newline at end of file | ||