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authorArnd Bergmann <arnd@arndb.de>2013-05-06 17:43:45 -0400
committerArnd Bergmann <arnd@arndb.de>2013-05-06 17:43:45 -0400
commit442a33ebce9e02a2dd6662f16c9f2aad834d0115 (patch)
treeca8654a286f61da917318645cab9e061095ecdba /Documentation/devicetree
parenta94d236dc355f374857ee4e6e78b7dec8a0f29e3 (diff)
parentf31c2f1c68aff83277eddc6798adf3438e9c680a (diff)
Merge branch 'late/clksrc' into late/cleanup
There is no reason to keep the clksrc cleanups separate from the other cleanups, and this resolves some merge conflicts. Conflicts: arch/arm/mach-spear/spear13xx.c drivers/irqchip/Makefile
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt67
-rw-r--r--Documentation/devicetree/bindings/bus/ti-gpmc.txt103
-rw-r--r--Documentation/devicetree/bindings/clock/axi-clkgen.txt22
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt303
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt44
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-vt8500.txt24
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt53
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-nor.txt98
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-onenand.txt3
-rw-r--r--Documentation/devicetree/bindings/net/gpmc-eth.txt97
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt57
-rw-r--r--Documentation/devicetree/bindings/timer/arm,sp804.txt29
-rw-r--r--Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt17
-rw-r--r--Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt68
15 files changed, 934 insertions, 55 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index b5846e21cc2e..1608a54e90e1 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -1,19 +1,84 @@
1NVIDIA Tegra Power Management Controller (PMC) 1NVIDIA Tegra Power Management Controller (PMC)
2 2
3Properties: 3The PMC block interacts with an external Power Management Unit. The PMC
4mostly controls the entry and exit of the system from different sleep
5modes. It provides power-gating controllers for SoC and CPU power-islands.
6
7Required properties:
4- name : Should be pmc 8- name : Should be pmc
5- compatible : Should contain "nvidia,tegra<chip>-pmc". 9- compatible : Should contain "nvidia,tegra<chip>-pmc".
6- reg : Offset and length of the register set for the device 10- reg : Offset and length of the register set for the device
11- clocks : Must contain an entry for each entry in clock-names.
12- clock-names : Must include the following entries:
13 "pclk" (The Tegra clock of that name),
14 "clk32k_in" (The 32KHz clock input to Tegra).
15
16Optional properties:
7- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. 17- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
8 The PMU is an external Power Management Unit, whose interrupt output 18 The PMU is an external Power Management Unit, whose interrupt output
9 signal is fed into the PMC. This signal is optionally inverted, and then 19 signal is fed into the PMC. This signal is optionally inverted, and then
10 fed into the ARM GIC. The PMC is not involved in the detection or 20 fed into the ARM GIC. The PMC is not involved in the detection or
11 handling of this interrupt signal, merely its inversion. 21 handling of this interrupt signal, merely its inversion.
22- nvidia,suspend-mode : The suspend mode that the platform should use.
23 Valid values are 0, 1 and 2:
24 0 (LP0): CPU + Core voltage off and DRAM in self-refresh
25 1 (LP1): CPU voltage off and DRAM in self-refresh
26 2 (LP2): CPU voltage off
27- nvidia,core-power-req-active-high : Boolean, core power request active-high
28- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
29- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
30- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
31 is enabled.
32
33Required properties when nvidia,suspend-mode is specified:
34- nvidia,cpu-pwr-good-time : CPU power good time in uS.
35- nvidia,cpu-pwr-off-time : CPU power off time in uS.
36- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
37 Core power good time in uS.
38- nvidia,core-pwr-off-time : Core power off time in uS.
39
40Required properties when nvidia,suspend-mode=<0>:
41- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
42 The LP0 vector contains the warm boot code that is executed by AVP when
43 resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
44 processor and always being the first boot processor when chip is power on
45 or resume from deep sleep mode. When the system is resumed from the deep
46 sleep mode, the warm boot code will restore some PLLs, clocks and then
47 bring up CPU0 for resuming the system.
12 48
13Example: 49Example:
14 50
51/ SoC dts including file
15pmc@7000f400 { 52pmc@7000f400 {
16 compatible = "nvidia,tegra20-pmc"; 53 compatible = "nvidia,tegra20-pmc";
17 reg = <0x7000e400 0x400>; 54 reg = <0x7000e400 0x400>;
55 clocks = <&tegra_car 110>, <&clk32k_in>;
56 clock-names = "pclk", "clk32k_in";
18 nvidia,invert-interrupt; 57 nvidia,invert-interrupt;
58 nvidia,suspend-mode = <1>;
59 nvidia,cpu-pwr-good-time = <2000>;
60 nvidia,cpu-pwr-off-time = <100>;
61 nvidia,core-pwr-good-time = <3845 3845>;
62 nvidia,core-pwr-off-time = <458>;
63 nvidia,core-power-req-active-high;
64 nvidia,sys-clock-req-active-high;
65 nvidia,lp0-vec = <0xbdffd000 0x2000>;
66};
67
68/ Tegra board dts file
69{
70 ...
71 clocks {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 clk32k_in: clock {
77 compatible = "fixed-clock";
78 reg=<0>;
79 #clock-cells = <0>;
80 clock-frequency = <32768>;
81 };
82 };
83 ...
19}; 84};
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 5ddb2e9efaaa..4b87ea1194e3 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -35,36 +35,83 @@ Required properties:
35 35
36Timing properties for child nodes. All are optional and default to 0. 36Timing properties for child nodes. All are optional and default to 0.
37 37
38 - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds 38 - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
39 39
40 Chip-select signal timings corresponding to GPMC_CONFIG2: 40 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
41 - gpmc,cs-on: Assertion time 41 - gpmc,cs-on-ns: Assertion time
42 - gpmc,cs-rd-off: Read deassertion time 42 - gpmc,cs-rd-off-ns: Read deassertion time
43 - gpmc,cs-wr-off: Write deassertion time 43 - gpmc,cs-wr-off-ns: Write deassertion time
44 44
45 ADV signal timings corresponding to GPMC_CONFIG3: 45 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
46 - gpmc,adv-on: Assertion time 46 - gpmc,adv-on-ns: Assertion time
47 - gpmc,adv-rd-off: Read deassertion time 47 - gpmc,adv-rd-off-ns: Read deassertion time
48 - gpmc,adv-wr-off: Write deassertion time 48 - gpmc,adv-wr-off-ns: Write deassertion time
49 49
50 WE signals timings corresponding to GPMC_CONFIG4: 50 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
51 - gpmc,we-on: Assertion time 51 - gpmc,we-on-ns Assertion time
52 - gpmc,we-off: Deassertion time 52 - gpmc,we-off-ns: Deassertion time
53 53
54 OE signals timings corresponding to GPMC_CONFIG4: 54 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
55 - gpmc,oe-on: Assertion time 55 - gpmc,oe-on-ns: Assertion time
56 - gpmc,oe-off: Deassertion time 56 - gpmc,oe-off-ns: Deassertion time
57 57
58 Access time and cycle time timings corresponding to GPMC_CONFIG5: 58 Access time and cycle time timings (in nanoseconds) corresponding to
59 - gpmc,page-burst-access: Multiple access word delay 59 GPMC_CONFIG5:
60 - gpmc,access: Start-cycle to first data valid delay 60 - gpmc,page-burst-access-ns: Multiple access word delay
61 - gpmc,rd-cycle: Total read cycle time 61 - gpmc,access-ns: Start-cycle to first data valid delay
62 - gpmc,wr-cycle: Total write cycle time 62 - gpmc,rd-cycle-ns: Total read cycle time
63 - gpmc,wr-cycle-ns: Total write cycle time
64 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
65 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
66 - gpmc,clk-activation-ns: GPMC clock activation time
67 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
68 data
69
70Boolean timing parameters. If property is present parameter enabled and
71disabled if omitted:
72 - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
73 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
74 - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
75 accesses to a different CS
76 - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
77 accesses to the same CS
78 - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
79 - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
80 - gpmc,time-para-granularity: Multiply all access times by 2
63 81
64The following are only applicable to OMAP3+ and AM335x: 82The following are only applicable to OMAP3+ and AM335x:
65 - gpmc,wr-access 83 - gpmc,wr-access-ns: In synchronous write mode, for single or
66 - gpmc,wr-data-mux-bus 84 burst accesses, defines the number of
67 85 GPMC_FCLK cycles from start access time
86 to the GPMC_CLK rising edge used by the
87 memory device for the first data capture.
88 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
89 the time when the first data is driven on
90 the address-data bus.
91
92GPMC chip-select settings properties for child nodes. All are optional.
93
94- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
95- gpmc,burst-wrap Enables wrap bursting
96- gpmc,burst-read Enables read page/burst mode
97- gpmc,burst-write Enables write page/burst mode
98- gpmc,device-nand Device is NAND
99- gpmc,device-width Total width of device(s) connected to a GPMC
100 chip-select in bytes. The GPMC supports 8-bit
101 and 16-bit devices and so this property must be
102 1 or 2.
103- gpmc,mux-add-data Address and data multiplexing configuration.
104 Valid values are 1 for address-address-data
105 multiplexing mode and 2 for address-data
106 multiplexing mode.
107- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
108 is this is not set.
109- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
110 is this is not set.
111- gpmc,wait-pin Wait-pin used by client. Must be less than
112 "gpmc,num-waitpins".
113- gpmc,wait-on-read Enables wait monitoring on reads.
114- gpmc,wait-on-write Enables wait monitoring on writes.
68 115
69Example for an AM33xx board: 116Example for an AM33xx board:
70 117
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
new file mode 100644
index 000000000000..028b493e97ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -0,0 +1,22 @@
1Binding for the axi-clkgen clock generator
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be "adi,axi-clkgen".
9- #clock-cells : from common clock binding; Should always be set to 0.
10- reg : Address and length of the axi-clkgen register set.
11- clocks : Phandle and clock specifier for the parent clock.
12
13Optional properties:
14- clock-output-names : From common clock binding.
15
16Example:
17 clock@0xff000000 {
18 compatible = "adi,axi-clkgen";
19 #clock-cells = <0>;
20 reg = <0xff000000 0x1000>;
21 clocks = <&osc 1>;
22 };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
new file mode 100644
index 000000000000..d6cb083b90a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -0,0 +1,303 @@
1NVIDIA Tegra114 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra114-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
27
28 0 unassigned
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 unassigned
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 unassigned
60
61 32 unassigned
62 33 unassigned
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 unassigned
67 38 unassigned
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned
79 50 mipi
80 51 hdmi
81 52 csi
82 53 unassigned
83 54 i2c2
84 55 uartc
85 56 mipi-cal
86 57 emc
87 58 usb2
88 59 usb3
89 60 msenc
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 unassigned
95 65 uartd
96 66 unassigned
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 unassigned
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 unassigned
106 76 la
107 77 trace
108 78 soc_therm
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 tsec
114 84 unassigned
115 85 unassigned
116 86 unassigned
117 87 unassigned
118 88 unassigned
119 89 xusb_host
120 90 unassigned
121 91 msenc
122 92 csus
123 93 unassigned
124 94 unassigned
125 95 unassigned (bit affects xusb_dev and xusb_dev_src)
126
127 96 unassigned
128 97 unassigned
129 98 unassigned
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 unassigned
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 spdif_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 unassigned
155 124 unassigned
156 125 hda
157 126 unassigned
158 127 se
159
160 128 hda2hdmi
161 129 unassigned
162 130 unassigned
163 131 unassigned
164 132 unassigned
165 133 unassigned
166 134 unassigned
167 135 unassigned
168 136 unassigned
169 137 unassigned
170 138 unassigned
171 139 unassigned
172 140 unassigned
173 141 unassigned
174 142 unassigned
175 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
176 xusb_host_src and xusb_ss_src)
177 144 cilab
178 145 cilcd
179 146 cile
180 147 dsialp
181 148 dsiblp
182 149 unassigned
183 150 dds
184 151 unassigned
185 152 dp2
186 153 amx
187 154 adx
188 155 unassigned (bit affects dfll_ref and dfll_soc)
189 156 xusb_ss
190
191 192 uartb
192 193 vfir
193 194 spdif_in
194 195 spdif_out
195 196 vi
196 197 vi_sensor
197 198 fuse
198 199 fuse_burn
199 200 clk_32k
200 201 clk_m
201 202 clk_m_div2
202 203 clk_m_div4
203 204 pll_ref
204 205 pll_c
205 206 pll_c_out1
206 207 pll_c2
207 208 pll_c3
208 209 pll_m
209 210 pll_m_out1
210 211 pll_p
211 212 pll_p_out1
212 213 pll_p_out2
213 214 pll_p_out3
214 215 pll_p_out4
215 216 pll_a
216 217 pll_a_out0
217 218 pll_d
218 219 pll_d_out0
219 220 pll_d2
220 221 pll_d2_out0
221 222 pll_u
222 223 pll_u_480M
223 224 pll_u_60M
224 225 pll_u_48M
225 226 pll_u_12M
226 227 pll_x
227 228 pll_x_out0
228 229 pll_re_vco
229 230 pll_re_out
230 231 pll_e_out0
231 232 spdif_in_sync
232 233 i2s0_sync
233 234 i2s1_sync
234 235 i2s2_sync
235 236 i2s3_sync
236 237 i2s4_sync
237 238 vimclk_sync
238 239 audio0
239 240 audio1
240 241 audio2
241 242 audio3
242 243 audio4
243 244 spdif
244 245 clk_out_1
245 246 clk_out_2
246 247 clk_out_3
247 248 blink
248 252 xusb_host_src
249 253 xusb_falcon_src
250 254 xusb_fs_src
251 255 xusb_ss_src
252 256 xusb_dev_src
253 257 xusb_dev
254 258 xusb_hs_src
255 259 sclk
256 260 hclk
257 261 pclk
258 262 cclk_g
259 263 cclk_lp
260 264 dfll_ref
261 265 dfll_soc
262
263Example SoC include file:
264
265/ {
266 tegra_car: clock {
267 compatible = "nvidia,tegra114-car";
268 reg = <0x60006000 0x1000>;
269 #clock-cells = <1>;
270 };
271
272 usb@c5004000 {
273 clocks = <&tegra_car 58>; /* usb2 */
274 };
275};
276
277Example board file:
278
279/ {
280 clocks {
281 compatible = "simple-bus";
282 #address-cells = <1>;
283 #size-cells = <0>;
284
285 osc: clock@0 {
286 compatible = "fixed-clock";
287 reg = <0>;
288 #clock-cells = <0>;
289 clock-frequency = <12000000>;
290 };
291
292 clk_32k: clock@1 {
293 compatible = "fixed-clock";
294 reg = <1>;
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 };
298 };
299
300 &tegra_car {
301 clocks = <&clk_32k> <&osc>;
302 };
303};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac73528..e885680f6b45 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
120 90 clk_d 120 90 clk_d
121 91 unassigned 121 91 unassigned
122 92 sus 122 92 sus
123 93 cdev1 123 93 cdev2
124 94 cdev2 124 94 cdev1
125 95 unassigned 125 95 unassigned
126 126
127 96 uart2 127 96 uart2
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 000000000000..20b8479c2760
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,44 @@
1Device Tree Clock bindings for arch-sunxi
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-ahb-clk" - for the AHB clock
14 "allwinner,sun4i-apb0-clk" - for the APB0 clock
15 "allwinner,sun4i-apb1-clk" - for the APB1 clock
16 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
17
18Required properties for all clocks:
19- reg : shall be the control register address for the clock.
20- clocks : shall be the input parent clock(s) phandle for the clock
21- #clock-cells : from common clock binding; shall be set to 0.
22
23For example:
24
25osc24M: osc24M@01c20050 {
26 #clock-cells = <0>;
27 compatible = "allwinner,sun4i-osc-clk";
28 reg = <0x01c20050 0x4>;
29 clocks = <&osc24M_fixed>;
30};
31
32pll1: pll1@01c20000 {
33 #clock-cells = <0>;
34 compatible = "allwinner,sun4i-pll1-clk";
35 reg = <0x01c20000 0x4>;
36 clocks = <&osc24M>;
37};
38
39cpu: cpu@01c20054 {
40 #clock-cells = <0>;
41 compatible = "allwinner,sun4i-cpu-clk";
42 reg = <0x01c20054 0x4>;
43 clocks = <&osc32k>, <&osc24M>, <&pll1>;
44};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
deleted file mode 100644
index f4dc5233167e..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
+++ /dev/null
@@ -1,24 +0,0 @@
1VIA/Wondermedia VT8500 GPIO Controller
2-----------------------------------------------------
3
4Required properties:
5- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
6 or "wm,wm8650-gpio" depending on your SoC
7- reg : Should contain 1 register range (address and length)
8- #gpio-cells : should be <3>.
9 1) bank
10 2) pin number
11 3) flags - should be 0
12
13Example:
14
15 gpio: gpio-controller@d8110000 {
16 compatible = "via,vt8500-gpio";
17 gpio-controller;
18 reg = <0xd8110000 0x10000>;
19 #gpio-cells = <3>;
20 };
21
22 vibrate {
23 gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
24 };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
new file mode 100644
index 000000000000..c54c5a9a2a90
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
@@ -0,0 +1,53 @@
1Samsung S3C24XX Interrupt Controllers
2
3The S3C24XX SoCs contain a custom set of interrupt controllers providing a
4varying number of interrupt sources. The set consists of a main- and sub-
5controller and on newer SoCs even a second main controller.
6
7Required properties:
8- compatible: Compatible property value should be "samsung,s3c2410-irq"
9 for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
10
11- reg: Physical base address of the controller and length of memory mapped
12 region.
13
14- interrupt-controller : Identifies the node as an interrupt controller
15
16- #interrupt-cells : Specifies the number of cells needed to encode an
17 interrupt source. The value shall be 4 and interrupt descriptor shall
18 have the following format:
19 <ctrl_num parent_irq ctrl_irq type>
20
21 ctrl_num contains the controller to use:
22 - 0 ... main controller
23 - 1 ... sub controller
24 - 2 ... second main controller on s3c2416 and s3c2450
25 parent_irq contains the parent bit in the main controller and will be
26 ignored in main controllers
27 ctrl_irq contains the interrupt bit of the controller
28 type contains the trigger type to use
29
30Example:
31
32 interrupt-controller@4a000000 {
33 compatible = "samsung,s3c2410-irq";
34 reg = <0x4a000000 0x100>;
35 interrupt-controller;
36 #interrupt-cells=<4>;
37 };
38
39 [...]
40
41 serial@50000000 {
42 compatible = "samsung,s3c2410-uart";
43 reg = <0x50000000 0x4000>;
44 interrupt-parent = <&subintc>;
45 interrupts = <1 28 0 4>, <1 28 1 4>;
46 };
47
48 rtc@57000000 {
49 compatible = "samsung,s3c2410-rtc";
50 reg = <0x57000000 0x100>;
51 interrupt-parent = <&intc>;
52 interrupts = <0 30 0 3>, <0 8 0 3>;
53 };
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
new file mode 100644
index 000000000000..420b3ab18890
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
@@ -0,0 +1,98 @@
1Device tree bindings for NOR flash connect to TI GPMC
2
3NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
4child nodes of the GPMC controller with a name of "nor".
5
6All timing relevant properties as well as generic GPMC child properties are
7explained in a separate documents. Please refer to
8Documentation/devicetree/bindings/bus/ti-gpmc.txt
9
10Required properties:
11- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14- gpmc,cs-on-ns: Chip-select assertion time
15- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17- gpmc,oe-on-ns: Output-enable assertion time
18- gpmc,oe-off-ns: Output-enable de-assertion time
19- gpmc,we-on-ns Write-enable assertion time
20- gpmc,we-off-ns: Write-enable de-assertion time
21- gpmc,access-ns: Start cycle to first data capture (read access)
22- gpmc,rd-cycle-ns: Total read cycle time
23- gpmc,wr-cycle-ns: Total write cycle time
24- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
25- reg: Chip-select, base address (relative to chip-select)
26 and size of NOR flash. Note that base address will be
27 typically 0 as this is the start of the chip-select.
28
29Optional properties:
30- gpmc,XXX Additional GPMC timings and settings parameters. See
31 Documentation/devicetree/bindings/bus/ti-gpmc.txt
32
33Optional properties for partiton table parsing:
34- #address-cells: should be set to 1
35- #size-cells: should be set to 1
36
37Example:
38
39gpmc: gpmc@6e000000 {
40 compatible = "ti,omap3430-gpmc", "simple-bus";
41 ti,hwmods = "gpmc";
42 reg = <0x6e000000 0x1000>;
43 interrupts = <20>;
44 gpmc,num-cs = <8>;
45 gpmc,num-waitpins = <4>;
46 #address-cells = <2>;
47 #size-cells = <1>;
48
49 ranges = <0 0 0x10000000 0x08000000>;
50
51 nor@0,0 {
52 compatible = "cfi-flash";
53 linux,mtd-name= "intel,pf48f6000m0y1be";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0 0 0x08000000>;
57 bank-width = <2>;
58
59 gpmc,mux-add-data;
60 gpmc,cs-on-ns = <0>;
61 gpmc,cs-rd-off-ns = <186>;
62 gpmc,cs-wr-off-ns = <186>;
63 gpmc,adv-on-ns = <12>;
64 gpmc,adv-rd-off-ns = <48>;
65 gpmc,adv-wr-off-ns = <48>;
66 gpmc,oe-on-ns = <54>;
67 gpmc,oe-off-ns = <168>;
68 gpmc,we-on-ns = <54>;
69 gpmc,we-off-ns = <168>;
70 gpmc,rd-cycle-ns = <186>;
71 gpmc,wr-cycle-ns = <186>;
72 gpmc,access-ns = <114>;
73 gpmc,page-burst-access-ns = <6>;
74 gpmc,bus-turnaround-ns = <12>;
75 gpmc,cycle2cycle-delay-ns = <18>;
76 gpmc,wr-data-mux-bus-ns = <90>;
77 gpmc,wr-access-ns = <186>;
78 gpmc,cycle2cycle-samecsen;
79 gpmc,cycle2cycle-diffcsen;
80
81 partition@0 {
82 label = "bootloader-nor";
83 reg = <0 0x40000>;
84 };
85 partition@0x40000 {
86 label = "params-nor";
87 reg = <0x40000 0x40000>;
88 };
89 partition@0x80000 {
90 label = "kernel-nor";
91 reg = <0x80000 0x200000>;
92 };
93 partition@0x280000 {
94 label = "filesystem-nor";
95 reg = <0x240000 0x7d80000>;
96 };
97 };
98};
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index deec9da224a2..b7529424ac88 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
10Required properties: 10Required properties:
11 11
12 - reg: The CS line the peripheral is connected to 12 - reg: The CS line the peripheral is connected to
13 - gpmc,device-width Width of the ONENAND device connected to the GPMC
14 in bytes. Must be 1 or 2.
13 15
14Optional properties: 16Optional properties:
15 17
@@ -34,6 +36,7 @@ Example for an OMAP3430 board:
34 36
35 onenand@0 { 37 onenand@0 {
36 reg = <0 0 0>; /* CS0, offset 0 */ 38 reg = <0 0 0>; /* CS0, offset 0 */
39 gpmc,device-width = <2>;
37 40
38 #address-cells = <1>; 41 #address-cells = <1>;
39 #size-cells = <1>; 42 #size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt
new file mode 100644
index 000000000000..24cb4e46f675
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/gpmc-eth.txt
@@ -0,0 +1,97 @@
1Device tree bindings for Ethernet chip connected to TI GPMC
2
3Besides being used to interface with external memory devices, the
4General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5such as ethernet controllers to processors using the TI GPMC as a data bus.
6
7Ethernet controllers connected to TI GPMC are represented as child nodes of
8the GPMC controller with an "ethernet" name.
9
10All timing relevant properties as well as generic GPMC child properties are
11explained in a separate documents. Please refer to
12Documentation/devicetree/bindings/bus/ti-gpmc.txt
13
14For the properties relevant to the ethernet controller connected to the GPMC
15refer to the binding documentation of the device. For example, the documentation
16for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
17
18Child nodes need to specify the GPMC bus address width using the "bank-width"
19property but is possible that an ethernet controller also has a property to
20specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21address width, it supports devices with 32-bit word registers.
22For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
23OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
24
25Required properties:
26- bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28- compatible: Compatible string property for the ethernet child device.
29- gpmc,cs-on: Chip-select assertion time
30- gpmc,cs-rd-off: Chip-select de-assertion time for reads
31- gpmc,cs-wr-off: Chip-select de-assertion time for writes
32- gpmc,oe-on: Output-enable assertion time
33- gpmc,oe-off Output-enable de-assertion time
34- gpmc,we-on: Write-enable assertion time
35- gpmc,we-off: Write-enable de-assertion time
36- gpmc,access: Start cycle to first data capture (read access)
37- gpmc,rd-cycle: Total read cycle time
38- gpmc,wr-cycle: Total write cycle time
39- reg: Chip-select, base address (relative to chip-select)
40 and size of the memory mapped for the device.
41 Note that base address will be typically 0 as this
42 is the start of the chip-select.
43
44Optional properties:
45- gpmc,XXX Additional GPMC timings and settings parameters. See
46 Documentation/devicetree/bindings/bus/ti-gpmc.txt
47
48Example:
49
50gpmc: gpmc@6e000000 {
51 compatible = "ti,omap3430-gpmc";
52 ti,hwmods = "gpmc";
53 reg = <0x6e000000 0x1000>;
54 interrupts = <20>;
55 gpmc,num-cs = <8>;
56 gpmc,num-waitpins = <4>;
57 #address-cells = <2>;
58 #size-cells = <1>;
59
60 ranges = <5 0 0x2c000000 0x1000000>;
61
62 ethernet@5,0 {
63 compatible = "smsc,lan9221", "smsc,lan9115";
64 reg = <5 0 0xff>;
65 bank-width = <2>;
66
67 gpmc,mux-add-data;
68 gpmc,cs-on = <0>;
69 gpmc,cs-rd-off = <186>;
70 gpmc,cs-wr-off = <186>;
71 gpmc,adv-on = <12>;
72 gpmc,adv-rd-off = <48>;
73 gpmc,adv-wr-off = <48>;
74 gpmc,oe-on = <54>;
75 gpmc,oe-off = <168>;
76 gpmc,we-on = <54>;
77 gpmc,we-off = <168>;
78 gpmc,rd-cycle = <186>;
79 gpmc,wr-cycle = <186>;
80 gpmc,access = <114>;
81 gpmc,page-burst-access = <6>;
82 gpmc,bus-turnaround = <12>;
83 gpmc,cycle2cycle-delay = <18>;
84 gpmc,wr-data-mux-bus = <90>;
85 gpmc,wr-access = <186>;
86 gpmc,cycle2cycle-samecsen;
87 gpmc,cycle2cycle-diffcsen;
88
89 interrupt-parent = <&gpio6>;
90 interrupts = <16>;
91 vmmc-supply = <&vddvario>;
92 vmmc_aux-supply = <&vdd33a>;
93 reg-io-width = <4>;
94
95 smsc,save-mac-address;
96 };
97};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
new file mode 100644
index 000000000000..b3aa90f0ce44
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
@@ -0,0 +1,57 @@
1VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
2
3These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
4either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
5
6Required properties:
7- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9- reg: Should contain the physical address of the module's registers.
10- interrupt-controller: Marks the device node as an interrupt controller.
11- #interrupt-cells: Should be two.
12- gpio-controller: Marks the device node as a GPIO controller.
13- #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters.
15 bit 0 - active low
16
17Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
18
19Please refer to pinctrl-bindings.txt in this directory for details of the
20common pinctrl bindings used by client devices, including the meaning of the
21phrase "pin configuration node".
22
23Each pin configuration node lists the pin(s) to which it applies, and one or
24more of the mux functions to select on those pin(s), and pull-up/down
25configuration. Each subnode only affects those parameters that are explicitly
26listed. In other words, a subnode that lists only a mux function implies no
27information about any pull configuration. Similarly, a subnode that lists only
28a pull parameter implies no information about the mux function.
29
30Required subnode-properties:
31- wm,pins: An array of cells. Each cell contains the ID of a pin.
32
33Optional subnode-properties:
34- wm,function: Integer, containing the function to mux to the pin(s):
35 0: GPIO in
36 1: GPIO out
37 2: alternate
38
39- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
40 0: none
41 1: down
42 2: up
43
44Each of wm,function and wm,pull may contain either a single value which
45will be applied to all pins in wm,pins, or one value for each entry in
46wm,pins.
47
48Example:
49
50 pinctrl: pinctrl {
51 compatible = "wm,wm8505-pinctrl";
52 reg = <0xD8110000 0x10000>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt
new file mode 100644
index 000000000000..5cd8eee74af1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt
@@ -0,0 +1,29 @@
1ARM sp804 Dual Timers
2---------------------------------------
3
4Required properties:
5- compatible: Should be "arm,sp804" & "arm,primecell"
6- interrupts: Should contain the list of Dual Timer interrupts. This is the
7 interrupt for timer 1 and timer 2. In the case of a single entry, it is
8 the combined interrupt or if "arm,sp804-has-irq" is present that
9 specifies which timer interrupt is connected.
10- reg: Should contain location and length for dual timer register.
11- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
12 clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
13 apb_pclk. A single clock can also be specified if the same clock is
14 used for all clock inputs.
15
16Optional properties:
17- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
18 specifies if the irq connection is for timer 1 or timer 2. A value of 1
19 or 2 should be used.
20
21Example:
22
23 timer0: timer@fc800000 {
24 compatible = "arm,sp804", "arm,primecell";
25 reg = <0xfc800000 0x1000>;
26 interrupts = <0 0 4>, <0 1 4>;
27 clocks = <&timclk1 &timclk2 &pclk>;
28 clock-names = "timer1", "timer2", "apb_pclk";
29 };
diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
new file mode 100644
index 000000000000..993695c659e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
@@ -0,0 +1,17 @@
1Cadence TTC - Triple Timer Counter
2
3Required properties:
4- compatible : Should be "cdns,ttc".
5- reg : Specifies base physical address and size of the registers.
6- interrupts : A list of 3 interrupts; one per timer channel.
7- clocks: phandle to the source clock
8
9Example:
10
11ttc0: ttc0@f8001000 {
12 interrupt-parent = <&intc>;
13 interrupts = < 0 10 4 0 11 4 0 12 4 >;
14 compatible = "cdns,ttc";
15 reg = <0xF8001000 0x1000>;
16 clocks = <&cpu_clk 3>;
17};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000000000000..cb47bfbcaeea
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,68 @@
1Samsung's Multi Core Timer (MCT)
2
3The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
4global timer and CPU local timers. The global timer is a 64-bit free running
5up-counter and can generate 4 interrupts when the counter reaches one of the
6four preset counter values. The CPU local timers are 32-bit free running
7down-counters and generate an interrupt when the counter expires. There is
8one CPU local timer instantiated in MCT for every CPU in the system.
9
10Required properties:
11
12- compatible: should be "samsung,exynos4210-mct".
13 (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
14 (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
15
16- reg: base address of the mct controller and length of the address space
17 it occupies.
18
19- interrupts: the list of interrupts generated by the controller. The following
20 should be the order of the interrupts specified. The local timer interrupts
21 should be specified after the four global timer interrupts have been
22 specified.
23
24 0: Global Timer Interrupt 0
25 1: Global Timer Interrupt 1
26 2: Global Timer Interrupt 2
27 3: Global Timer Interrupt 3
28 4: Local Timer Interrupt 0
29 5: Local Timer Interrupt 1
30 6: ..
31 7: ..
32 i: Local Timer Interrupt n
33
34Example 1: In this example, the system uses only the first global timer
35 interrupt generated by MCT and the remaining three global timer
36 interrupts are unused. Two local timer interrupts have been
37 specified.
38
39 mct@10050000 {
40 compatible = "samsung,exynos4210-mct";
41 reg = <0x10050000 0x800>;
42 interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
43 <0 42 0>, <0 48 0>;
44 };
45
46Example 2: In this example, the MCT global and local timer interrupts are
47 connected to two seperate interrupt controllers. Hence, an
48 interrupt-map is created to map the interrupts to the respective
49 interrupt controllers.
50
51 mct@101C0000 {
52 compatible = "samsung,exynos4210-mct";
53 reg = <0x101C0000 0x800>;
54 interrupt-controller;
55 #interrups-cells = <2>;
56 interrupt-parent = <&mct_map>;
57 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
58 <4 0>, <5 0>;
59
60 mct_map: mct-map {
61 #interrupt-cells = <2>;
62 #address-cells = <0>;
63 #size-cells = <0>;
64 interrupt-map = <0x0 0 &combiner 23 3>,
65 <0x4 0 &gic 0 120 0>,
66 <0x5 0 &gic 0 121 0>;
67 };
68 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:32:10 -0500