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authorTony Prisk <linux@prisktech.co.nz>2013-02-19 15:32:19 -0500
committerTony Prisk <linux@prisktech.co.nz>2013-04-04 01:00:02 -0400
commit170c6152aebc5538db22dbdf56fba11ccba7a6f4 (patch)
tree66443f64de630e68507f9b52b881ec6ffd804d47 /Documentation/devicetree/bindings/pinctrl
parent01bb914c8a91df82978b25d9b244945c79c1c632 (diff)
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
This patch adds support for the GPIO/pinmux controller found on the VIA VT8500 and Wondermedia WM8xxx-series SoCs. Each pin within the controller is capable of operating as a GPIO or as an alternate function. The pins are numbered according to their control bank/bit so that if new pins are added, the existing numbering is maintained. All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and WM8850. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
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1VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
2
3These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
4either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
5
6Required properties:
7- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9- reg: Should contain the physical address of the module's registers.
10- interrupt-controller: Marks the device node as an interrupt controller.
11- #interrupt-cells: Should be two.
12- gpio-controller: Marks the device node as a GPIO controller.
13- #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters.
15 bit 0 - active low
16
17Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
18
19Please refer to pinctrl-bindings.txt in this directory for details of the
20common pinctrl bindings used by client devices, including the meaning of the
21phrase "pin configuration node".
22
23Each pin configuration node lists the pin(s) to which it applies, and one or
24more of the mux functions to select on those pin(s), and pull-up/down
25configuration. Each subnode only affects those parameters that are explicitly
26listed. In other words, a subnode that lists only a mux function implies no
27information about any pull configuration. Similarly, a subnode that lists only
28a pull parameter implies no information about the mux function.
29
30Required subnode-properties:
31- wm,pins: An array of cells. Each cell contains the ID of a pin.
32
33Optional subnode-properties:
34- wm,function: Integer, containing the function to mux to the pin(s):
35 0: GPIO in
36 1: GPIO out
37 2: alternate
38
39- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
40 0: none
41 1: down
42 2: up
43
44Each of wm,function and wm,pull may contain either a single value which
45will be applied to all pins in wm,pins, or one value for each entry in
46wm,pins.
47
48Example:
49
50 pinctrl: pinctrl {
51 compatible = "wm,wm8505-pinctrl";
52 reg = <0xD8110000 0x10000>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 gpio-controller;
56 #gpio-cells = <2>;
57 };