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authorMichael Witten <mfwitten@gmail.com>2011-08-29 12:00:55 -0400
committerMichael Witten <mfwitten@gmail.com>2011-08-29 16:00:24 -0400
commit2d43f5d667273ba4975cb79782a46aa374dd8607 (patch)
treefed80399516beeb604ab9a99fc3074e25539a511 /Documentation/DocBook/drm.tmpl
parent0c2d91a80a156208d2f9f3dfb01871ebcf4a9338 (diff)
DocBook/drm: Improve flow of GPU/CPU coherence sentence
Signed-off-by: Michael Witten <mfwitten@gmail.com>
Diffstat (limited to 'Documentation/DocBook/drm.tmpl')
-rw-r--r--Documentation/DocBook/drm.tmpl5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index c358367f9f85..ba20f9fbb62b 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -720,8 +720,9 @@ void intel_crt_init(struct drm_device *dev)
720 provides memory to back each object. When mapped into the GTT 720 provides memory to back each object. When mapped into the GTT
721 or used in a command buffer, the backing pages for an object are 721 or used in a command buffer, the backing pages for an object are
722 flushed to memory and marked write combined so as to be coherent 722 flushed to memory and marked write combined so as to be coherent
723 with the GPU. Likewise, when the GPU finishes rendering to an object, 723 with the GPU. Likewise, if the CPU accesses an object after the GPU
724 if the CPU accesses it, it must be made coherent with the CPU's view 724 has finished rendering to the object, then the object must be made
725 coherent with the CPU's view
725 of memory, usually involving GPU cache flushing of various kinds. 726 of memory, usually involving GPU cache flushing of various kinds.
726 This core CPU&lt;-&gt;GPU coherency management is provided by the GEM 727 This core CPU&lt;-&gt;GPU coherency management is provided by the GEM
727 set domain function, which evaluates an object's current domain and 728 set domain function, which evaluates an object's current domain and