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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2011-01-11 00:11:20 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-17 23:45:10 -0500
commitff9531ec1caf0e062da132933e33878f94449274 (patch)
treebf2acee7352d3a9da4115d20bcaa959c03c3b464
parentc488a4731abb53aa1bab9fccd8a7472083159bfd (diff)
ARM: mach-shmobile: clock-sh7372: fixup pllc2 set_rate
This patch fixup 421b446abeec55bed1251fab80cb5c12be58b773 - Care clk->rate - Don't over write PLLC2 enable bit Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 9aa8d68d1a9c..e9731b5a73ed 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -234,7 +234,9 @@ static int pllc2_set_rate(struct clk *clk, unsigned long rate)
234 234
235 value = __raw_readl(PLLC2CR) & ~(0x3f << 24); 235 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
236 236
237 __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR); 237 __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
238
239 clk->rate = clk->freq_table[idx].frequency;
238 240
239 return 0; 241 return 0;
240} 242}