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authorGuenter Roeck <guenter.roeck@ericsson.com>2012-03-13 12:05:14 -0400
committerGuenter Roeck <guenter.roeck@ericsson.com>2012-03-14 12:17:03 -0400
commitfecfb64422d91a9621a3f96ab75c3a5f13e80b58 (patch)
treed0b7fb8922d0a8b0ead112b87ea377450fb5b1b7
parentc43524b580e9599ef0d16adbbc4aa7ae808276ae (diff)
hwmon: (zl6100) Enable interval between chip accesses for all chips
Intersil reports that all chips supported by the zl6100 driver require an interval between chip accesses, even ZL2004 and ZL6105 which were thought to be safe. Reported-by: Vivek Gani <vgani@intersil.com> Cc: stable@vger.kernel.org # 3.2+ Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
-rw-r--r--Documentation/hwmon/zl610014
-rw-r--r--drivers/hwmon/pmbus/zl6100.c12
2 files changed, 9 insertions, 17 deletions
diff --git a/Documentation/hwmon/zl6100 b/Documentation/hwmon/zl6100
index 51f76a189fee..a4e8d90f59f6 100644
--- a/Documentation/hwmon/zl6100
+++ b/Documentation/hwmon/zl6100
@@ -88,14 +88,12 @@ Module parameters
88delay 88delay
89----- 89-----
90 90
91Some Intersil/Zilker Labs DC-DC controllers require a minimum interval between 91Intersil/Zilker Labs DC-DC controllers require a minimum interval between I2C
92I2C bus accesses. According to Intersil, the minimum interval is 2 ms, though 92bus accesses. According to Intersil, the minimum interval is 2 ms, though 1 ms
931 ms appears to be sufficient and has not caused any problems in testing. 93appears to be sufficient and has not caused any problems in testing. The problem
94The problem is known to affect ZL6100, ZL2105, and ZL2008. It is known not to 94is known to affect all currently supported chips. For manual override, the
95affect ZL2004 and ZL6105. The driver automatically sets the interval to 1 ms 95driver provides a writeable module parameter, 'delay', which can be used to set
96except for ZL2004 and ZL6105. To enable manual override, the driver provides a 96the interval to a value between 0 and 65,535 microseconds.
97writeable module parameter, 'delay', which can be used to set the interval to
98a value between 0 and 65,535 microseconds.
99 97
100 98
101Sysfs entries 99Sysfs entries
diff --git a/drivers/hwmon/pmbus/zl6100.c b/drivers/hwmon/pmbus/zl6100.c
index 880b90cf4d32..e3e8420b7b81 100644
--- a/drivers/hwmon/pmbus/zl6100.c
+++ b/drivers/hwmon/pmbus/zl6100.c
@@ -200,17 +200,11 @@ static int zl6100_probe(struct i2c_client *client,
200 data->id = mid->driver_data; 200 data->id = mid->driver_data;
201 201
202 /* 202 /*
203 * ZL2005, ZL2008, ZL2105, and ZL6100 are known to require a wait time 203 * According to information from the chip vendor, all currently
204 * between I2C accesses. ZL2004 and ZL6105 are known to be safe. 204 * supported chips are known to require a wait time between I2C
205 * Other chips have not yet been tested. 205 * accesses.
206 *
207 * Only clear the wait time for chips known to be safe. The wait time
208 * can be cleared later for additional chips if tests show that it
209 * is not needed (in other words, better be safe than sorry).
210 */ 206 */
211 data->delay = delay; 207 data->delay = delay;
212 if (data->id == zl2004 || data->id == zl6105)
213 data->delay = 0;
214 208
215 /* 209 /*
216 * Since there was a direct I2C device access above, wait before 210 * Since there was a direct I2C device access above, wait before