diff options
author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 10:40:44 -0400 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 18:10:59 -0400 |
commit | fdcccbd804088eb96881c9f6532de04868f9dbc1 (patch) | |
tree | cdec0c69139e1a8a4f6577c8bc3c91e7ebcbf22e | |
parent | a26a029893096204f08a3ff5e262f99e1a75e273 (diff) |
clk: tegra: Workaround for Tegra114 MSENC problem
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r-- | drivers/clk/tegra/clk-periph-gate.c | 9 | ||||
-rw-r--r-- | drivers/clk/tegra/clk.h | 2 |
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index d87e1cece9fa..bafee9895a24 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c | |||
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); | |||
43 | 43 | ||
44 | #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32)) | 44 | #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32)) |
45 | 45 | ||
46 | #define LVL2_CLK_GATE_OVRE 0x554 | ||
47 | |||
46 | /* Peripheral gate clock ops */ | 48 | /* Peripheral gate clock ops */ |
47 | static int clk_periph_is_enabled(struct clk_hw *hw) | 49 | static int clk_periph_is_enabled(struct clk_hw *hw) |
48 | { | 50 | { |
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw) | |||
83 | } | 85 | } |
84 | } | 86 | } |
85 | 87 | ||
88 | if (gate->flags & TEGRA_PERIPH_WAR_1005168) { | ||
89 | writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); | ||
90 | writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); | ||
91 | udelay(1); | ||
92 | writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); | ||
93 | } | ||
94 | |||
86 | spin_unlock_irqrestore(&periph_ref_lock, flags); | 95 | spin_unlock_irqrestore(&periph_ref_lock, flags); |
87 | 96 | ||
88 | return 0; | 97 | return 0; |
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fd12b77c985d..fb48f0467b9d 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h | |||
@@ -358,6 +358,7 @@ struct tegra_clk_periph_regs { | |||
358 | * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the | 358 | * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the |
359 | * bus to flush the write operation in apb bus. This flag indicates | 359 | * bus to flush the write operation in apb bus. This flag indicates |
360 | * that this peripheral is in apb bus. | 360 | * that this peripheral is in apb bus. |
361 | * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug | ||
361 | */ | 362 | */ |
362 | struct tegra_clk_periph_gate { | 363 | struct tegra_clk_periph_gate { |
363 | u32 magic; | 364 | u32 magic; |
@@ -377,6 +378,7 @@ struct tegra_clk_periph_gate { | |||
377 | #define TEGRA_PERIPH_NO_RESET BIT(0) | 378 | #define TEGRA_PERIPH_NO_RESET BIT(0) |
378 | #define TEGRA_PERIPH_MANUAL_RESET BIT(1) | 379 | #define TEGRA_PERIPH_MANUAL_RESET BIT(1) |
379 | #define TEGRA_PERIPH_ON_APB BIT(2) | 380 | #define TEGRA_PERIPH_ON_APB BIT(2) |
381 | #define TEGRA_PERIPH_WAR_1005168 BIT(3) | ||
380 | 382 | ||
381 | void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); | 383 | void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); |
382 | extern const struct clk_ops tegra_clk_periph_gate_ops; | 384 | extern const struct clk_ops tegra_clk_periph_gate_ops; |